appease modelsim with illegible hdl

hdl/eb_usb_core/.gitignore

@@ -8,6 +8,7 @@ cdc_acm.omf
 cdc_acm.rel
 cdc_acm.rst
 cdc_acm.sym
+cdc_acm.ihx
 erase_eeprom.asm
 erase_eeprom.cdb
 erase_eeprom.lk
@@ -18,3 +19,4 @@ erase_eeprom.omf
 erase_eeprom.rel
 erase_eeprom.rst
 erase_eeprom.sym
+erase_eeprom.ihx
\ No newline at end of file

hdl/eb_usb_core/ez_usb.vhd

@@ -157,13 +157,13 @@ begin
       rstn_i       => rstn_i,
       
       slave_i(0)   => usb2eb_usb_i, -- EP2 (out) = host writes to EB
-      slave_o(0)   => usb2eb_usb_o,
+      slave_i(1)   => usb2uart_usb_i, -- EP4 (out) = host writes to uart
       slave_i(2)   => eb2usb_m,     -- EP6 (in)  = EB writes to host
-      slave_o(2)   => eb2usb_s,
+      slave_i(3)   => uart2usb_usb_i, -- EP8 (in)  = uart writes to host
       
-      slave_i(1)   => usb2uart_usb_i, -- EP4 (out) = host writes to uart
+      slave_o(0)   => usb2eb_usb_o,
       slave_o(1)   => usb2uart_usb_o,
-      slave_i(3)   => uart2usb_usb_i, -- EP8 (in)  = uart writes to host
+      slave_o(2)   => eb2usb_s,
       slave_o(3)   => uart2usb_usb_o,
       
       fifoadr_o    => fifoadr_o,