@@ -44,14 +44,14 @@ Wherever possible, the same components shall be used as in the [DI/OT ZU7 System
### Requirements
* The board shall have EEPROM-based identification mechanism implemented according to [Peripheral Boards identification procedure](https://ohwr.org/project/diot/wikis/crate_monitoring#peripheral-boards-identification)
* the same SERVMOD_N signal shall drive:
- analog switches to dynamically attach identification EEPROM to the backplane I2C bus
- multiplexers selecting P1 I/Os assigment between FPGA JTAG TAP and regular I/Os
- analog switches to dynamically attach identification EEPROM to the backplane I2C bus
- multiplexers selecting P1 I/Os assigment between FPGA JTAG TAP and regular I/Os
* Backplane P1 connector pins shall have dual IO/JTAG function (selectable with SERVMOD_N):
-*A3* - TDI
-*D3* - TDO
-*B4* - TMS
-*H4* - TCK
-*K4* - nTRST
-*A3* - TDI
-*D3* - TDO
-*B4* - TMS
-*H4* - TCK
-*K4* - nTRST
* MGT backplane lanes (P1.A5,A6,D5,E5) shall be connected to FPGA MGT
