adding simulation model for Pentair FCM2

758d6ea2 · Grzegorz Daniluk · 2c76ebe0 · 758d6ea2 · 758d6ea2 · 758d6ea2
Commit 758d6ea2 authored Aug 10, 2018 by Grzegorz Daniluk
9 changed files
--- a/hdl/sim/Manifest.py
+++ b/hdl/sim/Manifest.py
 files = [ "fip_device.svh", "fip_frame.svh", "fip_hardware_model.svh",
-        "fip_phy_model.svh", "fip_virtual_master.svh" ]
+        "fip_phy_model.svh", "fip_virtual_master.svh", "fcm2_interface.svh" ]

-module = {"local" : ["./i2cslave"]}
+include_dirs = [ "include", "include/wb" ]
+modules = {"local" : ["fcm2"]}
--- a/hdl/sim/fcm2/Manifest.py
+++ b/hdl/sim/fcm2/Manifest.py
+files = [ "pentair_fcm2_model.sv" ]
+
--- a/hdl/sim/fcm2/pentair_fcm2_model.sv
+++ b/hdl/sim/fcm2/pentair_fcm2_model.sv
+//-----------------------------------------------------------------------------
+// Title      : Pentair FCM2 simulation model
+// Project    : Distributed I/O Tier
+//-----------------------------------------------------------------------------
+// File       : pentair_fcm2_model.sv
+// Author     : Greg Daniluk <grzegorz.daniluk@cern.ch>
+// Company    : CERN (BE-CO-HT)
+// Standard   : VHDL
+//-----------------------------------------------------------------------------
+// Description:
+// This module is a simulation model for Pentair FCM2 diagnostics module. It
+// uses I2C slave implementation from general-cores repository and FCM_interface
+// to generate randomized monitoring data.
+//-----------------------------------------------------------------------------
+//
+// Copyright (c) 2018 CERN
+//
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the “License”) (which enables you, at your option,
+// to treat this file as licensed under the Apache License 2.0); you may not
+// use this file except in compliance with the License. You may obtain a copy
+// of the License at http://solderpad.org/licenses/SHL-0.51.
+// Unless required by applicable law or agreed to in writing, software,
+// hardware and materials distributed under this License is distributed on an
+// “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+// or implied. See the License for the specific language governing permissions
+// and limitations under the License.
+//
+//-----------------------------------------------------------------------------
+
+`include "../fcm2_interface.svh"
+
+module pentair_fcm2_model (clk_i, rst_n_i, sda_b, scl_b);
+  input clk_i;
+  input rst_n_i;
+  inout sda_b;
+  inout scl_b;
+
+  reg [7:0] fan_status;
+  reg [7:0] temp_status;
+  reg [7:0] volt_status;
+  reg [0:11] [7:0] fan_speed;
+
+  wire scl_out, scl_en;
+  wire sda_out, sda_en;
+
+  FCM_interface ctrl(clk_i, rst_n_i);
+
+  always @(posedge clk_i) begin
+    fan_status  = 'hCA;
+    temp_status = 'hFE;
+    volt_status = 'h01;
+    fan_speed   = 'hDEADBEEFBABE010203040506;
+  end
+
+  gc_i2c_slave #(
+    .g_auto_addr_ack(1))
+  i2c_slave (
+    .clk_i(clk_i),
+    .rst_n_i(rst_n_i),
+    .scl_i(scl_b),
+    .scl_o(scl_out),
+    .scl_en_o(scl_en),
+    .sda_i(sda_b),
+    .sda_o(sda_out),
+    .sda_en_o(sda_en),
+    .i2c_addr_i   (ctrl.dev_adr),
+    .ack_i        (ctrl.ack),
+    .tx_byte_i    (ctrl.tx_byte),
+    .rx_byte_o    (ctrl.rx_byte),
+    .i2c_sta_p_o  (ctrl.sta_p),
+    .i2c_sto_p_o  (ctrl.sto_p),
+    .addr_good_p_o(ctrl.adr_good_p),
+    .r_done_p_o   (ctrl.r_done),
+    .w_done_p_o   (ctrl.w_done)
+  );
+
+  assign scl_b = (scl_en)? scl_out : 'bz;
+  assign sda_b = (sda_en)? sda_out : 'bz;
+
+  always begin
+    ctrl.new_values();
+    ctrl.reply();
+  end
+
+endmodule
--- a/hdl/sim/fcm2_interface.svh
+++ b/hdl/sim/fcm2_interface.svh
+//-----------------------------------------------------------------------------
+// Title      : Pentair FCM2 simulation interface
+// Project    : Distributed I/O Tier
+//-----------------------------------------------------------------------------
+// File       : fcm2_interface.svh
+// Author     : Greg Daniluk <grzegorz.daniluk@cern.ch>
+// Company    : CERN (BE-CO-HT)
+// Standard   : VHDL
+//-----------------------------------------------------------------------------
+// Description:
+// This interface for FCM2 simulation model mimics Pentair FCM2 diagnostics
+// module using i2c_slave from general-cores repository.
+//-----------------------------------------------------------------------------
+//
+// Copyright (c) 2018 CERN
+//
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the “License”) (which enables you, at your option,
+// to treat this file as licensed under the Apache License 2.0); you may not
+// use this file except in compliance with the License. You may obtain a copy
+// of the License at http://solderpad.org/licenses/SHL-0.51.
+// Unless required by applicable law or agreed to in writing, software,
+// hardware and materials distributed under this License is distributed on an
+// “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+// or implied. See the License for the specific language governing permissions
+// and limitations under the License.
+//
+//-----------------------------------------------------------------------------
+//
+// FCM2 commands layout:
+// read i2c address: 0x39
+// cmd 0: fan  status (return 1 Byte)
+// cmd 1: temp status (return 1 Byte)
+// cmd 2: volt status (return 1 Byte)
+// cmd 3: fans speed  (return 12 Bytes) - 2B per fan
+// cmd 4: temperature (return 6 Bytes)  - 1B per sensor
+//
+//-----------------------------------------------------------------------------
+
+interface FCM_interface (input clk_i, rst_n_i);
+
+  logic [6:0] dev_adr;
+  logic ack;
+  logic [7:0] tx_byte;
+  logic [7:0] rx_byte;
+  wire sta_p;
+  wire sto_p;
+  wire adr_good_p;
+  wire r_done;
+  wire w_done;
+
+  reg [7:0] fan_status;
+  reg [7:0] temp_status;
+  reg [7:0] volt_status;
+  reg [0:11] [7:0] fan_speed;
+  reg [0:5] [7:0] temps;
+
+  // set default values on reset
+  initial begin
+    dev_adr = 7'h1c;
+    ack = 'b1;
+    tx_byte = 'h00;
+    fan_status  = 'hCA;
+    temp_status = 'hFE;
+    volt_status = 'hBE;
+    fan_speed = '{'h01, 'h02, 'h03, 'h04, 'h05, 'h06, 'h07, 'h08, 'h09, 'h0A,
+    'h0B, 'h0C};
+    temps = '{'h11, 'h12, 'h13, 'h14, 'h15, 'h16};
+  end
+
+  task new_values;
+  
+    randomize (fan_status);
+    randomize (temp_status);
+    randomize (volt_status);
+    randomize (fan_speed);
+    randomize (temps);
+
+  endtask : new_values
+
+  // main functionality of FCM2, provide apropriate data depending on requested
+  // command
+  task reply;
+
+    int cmd;
+
+    $display("Execute reply");
+    // react only on proper address
+    wait(adr_good_p)
+    @(posedge clk_i);
+    // get command index
+    wait(r_done)
+    @(posedge clk_i);
+    cmd = rx_byte;
+
+    case(cmd)
+      0: begin
+        $display("Providing data for cmd0");
+        tx_byte <= fan_status;
+      end
+
+      1: begin
+        $display("Providing data for cmd1");
+        tx_byte <= temp_status;
+      end
+
+      2: begin
+        $display("Providing data for cmd2");
+        tx_byte <= volt_status;
+      end
+
+      3: begin
+        $display("Providing data for cmd3");
+        for (int i=0; i<12; i++) begin
+          tx_byte <= fan_speed[i];
+          @(posedge w_done);
+        end
+        $display("Done");
+      end
+
+      4: begin
+        $display("Providing data for cmd4");
+        for (int i=0; i<6; i++) begin
+          tx_byte <= temps[i];
+          @(posedge w_done);
+        end
+        $display("Done");
+      end
+
+    endcase
+    
+  endtask : reply
+
+endinterface
--- a/hdl/sim/include/Manifest.py
+++ b/hdl/sim/include/Manifest.py
 files = [ "logger.svh", "masterfip-common.svh", "mock_turtle_driver.svh",
        "mt_cpu_csr_driver.svh", "mt_mqueue_host_driver.svh",
        "serializable.svh", "vhd_wishbone_master.svh", "wrn_cpu_csr_regs.vh" ]
+
+include_dirs = [ "wb" ]
--- a/hdl/testbench/spec_test/Manifest.py
+++ b/hdl/testbench/spec_test/Manifest.py
@@ -3,7 +3,7 @@ sim_tool = "modelsim"
 top_module = "main"

 vcom_opt = "-2008 -mixedsvvh l"
-vlog_opt = "+incdir+../../ip_cores/masterfip-gw/testbench/top_mt"
+vlog_opt = "+incdir+../../ip_cores/masterfip-gw/testbench/top_mt +incdir+../../sim"

 # create a fake proasic3 library needed by nanofip
 sim_pre_cmd = "vlib ../fake_proasic3; vmap proasic3 ../fake_proasic3"
@@ -13,7 +13,7 @@ files = ["sim_main.sv", "ram4k9.v" ]
 include_dirs = [ "../../sim", "../../sim/include", "../../sim/include/wb" ]

 modules = {
-        "local" : ["../../rtl", "../../top/spec_test",
+        "local" : ["../../sim/fcm2", "../../rtl", "../../top/spec_test",
        "../../ip_cores/nanofip-gateware/top",
        "../../ip_cores/general-cores/"]}
 #, "../../ip_cores/masterfip-gw/testbench/top_mt"]}
--- a/hdl/testbench/spec_test/run.do
+++ b/hdl/testbench/spec_test/run.do
-vsim work.main
+vsim -L unisim work.main -voptargs="+acc"
 do wave.do
-run -all
+run 12ms
+#run -all
+wave zoomfull
--- a/hdl/testbench/spec_test/sim_main.sv
+++ b/hdl/testbench/spec_test/sim_main.sv
@@ -60,7 +60,7 @@ module main;

  reg [7:0] nf_address = 8'h01;  // Substation data
  wire [2:0] nf_p3lgth;
-  wire diag_scl, diag_sda;
+  tri1 diag_scl, diag_sda;

  // power-on-reset
  reg rstpo_n = 0;
@@ -157,11 +157,10 @@ module main;

  pentair_fcm2_model sim_FCM2(
    .clk_i(wclk),
-    .rst_i(wb_rst),
+    .rst_n_i(rstpo_n),
    .sda_b(diag_sda),
    .scl_b(diag_scl));

-
 //------------------------------------------------
 //      HERER we start sending/receiving stuff
 //------------------------------------------------

--- a/hdl/testbench/spec_test/wave.do
+++ b/hdl/testbench/spec_test/wave.do