diot_diag: interface with i2c_master to read monitoring from Pentair FCM2

2c76ebe0 · Grzegorz Daniluk · ff53c0e2 · 2c76ebe0 · 2c76ebe0 · 2c76ebe0
Commit 2c76ebe0 authored Aug 10, 2018 by Grzegorz Daniluk
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Showing with 314 additions and 2 deletions

diag_pkg.vhd hdl/rtl/diot_diag/diag_pkg.vhd +10 -0

diot_diag.vhd hdl/rtl/diot_diag/diot_diag.vhd +299 -0

spec_top.vhd hdl/top/spec_test/spec_top.vhd +5 -2

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--- a/hdl/rtl/diot_diag/diag_pkg.vhd
+++ b/hdl/rtl/diot_diag/diag_pkg.vhd
@@ -7,6 +7,8 @@
 -- Company    : CERN (BE-CO-HT)
 -- Standard   : VHDL
 -------------------------------------------------------------------------------
+-- Description:
+-- This package defines types and constants used by diot_diag module.
 -------------------------------------------------------------------------------
 --
 -- Copyright (c) 2018 CERN
@@ -28,6 +30,12 @@ library ieee;
 use ieee.std_logic_1164.all;

 package diag_pkg is
+
+  constant c_CMD_FAN_STAT  : integer := 0;
+  constant c_CMD_TEMP_STAT : integer := 1;
+  constant c_CMD_VOLT_STAT : integer := 2;
+  constant c_CMD_FAN_SPEED : integer := 3;
+  constant c_CMD_TEMP      : integer := 4;
  
  type t_diag_out is record
    fan_status  : std_logic_vector(7 downto 0);
@@ -44,4 +52,6 @@ package diag_pkg is
    temp6       : std_logic_vector(7 downto 0);
  end record;

+  type t_diag_buf is array (natural range<>) of std_logic_vector(7 downto 0);
+
 end diag_pkg;
--- a/hdl/rtl/diot_diag/diot_diag.vhd
+++ b/hdl/rtl/diot_diag/diot_diag.vhd
--- a/hdl/top/spec_test/spec_top.vhd
+++ b/hdl/top/spec_test/spec_top.vhd
@@ -84,6 +84,7 @@ architecture rtl of spec_top is
  signal clk_sys_locked    : std_logic;
  signal rst_n             : std_logic;
  signal scl_out, sda_out  : std_logic;
+  signal scl_oen, sda_oen  : std_logic;

  signal slots_in  : t_wic_slot_in_array(c_SLOT_NUM-1 downto 0);
  signal slots_out : t_wic_slot_out_array(c_SLOT_NUM-1 downto 0);
@@ -206,13 +207,15 @@ begin
    rst_n_i => rst_n,
    clk_i   => clk_sys_25m,
    scl_o   => scl_out,
+    scl_oen => scl_oen,
    scl_i   => diag_scl_b,
    sda_o   => sda_out,
+    sda_oen => sda_oen,
    sda_i   => diag_sda_b,
    diags_o => diags_out);

-  diag_scl_b <= '0' when(scl_out = '0') else 'Z';
-  diag_sda_b <= '0' when(sda_out = '0') else 'Z';
+  diag_scl_b <= scl_out when scl_oen = '0' else 'Z';
+  diag_sda_b <= sda_out when sda_oen = '0' else 'Z';

 -------------------------------------------------------------------------------