Add proto testbenches for urv.

22e2c73c · Tristan Gingold · c5d13d4d · 22e2c73c · 22e2c73c · 22e2c73c
Commit 22e2c73c authored Feb 20, 2020 by Tristan Gingold
5 changed files
--- a/hdl/testbench/urv_fip_plc/Manifest.py
+++ b/hdl/testbench/urv_fip_plc/Manifest.py
+action = "simulation"
+sim_tool = "modelsim"
+top_module = "top_sim"
+
+#vcom_opt = "-2008 -mixedsvvh l"
+#vlog_opt = "+incdir+../../ip_cores/masterfip-gw/testbench/top_mt +incdir+../../sim"
+
+# create a fake proasic3 library needed by nanofip
+#sim_pre_cmd = "vlib ../fake_proasic3; vmap proasic3 ../fake_proasic3"
+
+files = ["../../syn/diot_urv_demo/top_sim.vhdl"]
+
+#include_dirs = [ "../../sim", "../../sim/include", "../../sim/include/wb" ]
+
+modules = {
+        "local" : ["../../top/diot_urv_demo"] }
--- a/hdl/testbench/urv_fip_plc/run.do
+++ b/hdl/testbench/urv_fip_plc/run.do
+vsim -novopt top_sim
+log -r *
+run 2us
--- a/hdl/testbench/urv_wic_test/Manifest.py
+++ b/hdl/testbench/urv_wic_test/Manifest.py
+action = "simulation"
+sim_tool = "modelsim"
+top_module = "main"
+
+#vcom_opt = "-2008 -mixedsvvh l"
+#vlog_opt = "+incdir+../../ip_cores/masterfip-gw/testbench/top_mt +incdir+../../sim"
+
+# create a fake proasic3 library needed by nanofip
+#sim_pre_cmd = "vlib ../fake_proasic3; vmap proasic3 ../fake_proasic3"
+
+files = ["sim_main.sv"]
+
+#include_dirs = [ "../../sim", "../../sim/include", "../../sim/include/wb" ]
+
+modules = {
+        "local" : ["../../top/diot_urv_demo"] }
--- a/hdl/testbench/urv_wic_test/run.do
+++ b/hdl/testbench/urv_wic_test/run.do
+vsim -novopt main
+log -r *
+run 2us
--- a/hdl/testbench/urv_wic_test/sim_main.sv
+++ b/hdl/testbench/urv_wic_test/sim_main.sv
+///////////////////////////////////////////////////////////////////////////////
+// Title      : Simple DIOT WIC testbench
+// Project    : Distributed I/O Tier
+///////////////////////////////////////////////////////////////////////////////
+// File       : sim_main.vhd
+// Author     : Greg Daniluk <grzegorz.daniluk@cern.ch>
+// Company    : CERN (BE-CO-HT)
+// Standard   : VHDL
+///////////////////////////////////////////////////////////////////////////////
+// Description:
+// Very first, quick and simple testbench for DIOT WIC gateware. More complete
+// testbench to be done.
+//
+///////////////////////////////////////////////////////////////////////////////
+//
+// Copyright (c) 2018 CERN
+//
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the “License”) (which enables you, at your option,
+// to treat this file as licensed under the Apache License 2.0); you may not
+// use this file except in compliance with the License. You may obtain a copy
+// of the License at http://solderpad.org/licenses/SHL-0.51.
+// Unless required by applicable law or agreed to in writing, software,
+// hardware and materials distributed under this License is distributed on an
+// “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+// or implied. See the License for the specific language governing permissions
+// and limitations under the License.
+//
+///////////////////////////////////////////////////////////////////////////////
+
+`timescale 1ns/1ps
+
+module main;
+
+  reg clk_25m = 0;
+  always #(20ns) clk_25m <= ~clk_25m;
+
+  wire [7:0] wb_dat_in;
+  wire [7:0] wb_dat_out;
+  wire [9:0] wb_adr;
+  wire wb_stb, wclk, wb_we, wb_cyc, wb_ack, wb_rst;
+  wire nf_var1_acc, nf_var2_acc, nf_var3_acc;
+  wire nf_var1_rdy, nf_var2_rdy, nf_var3_rdy;
+  wire nf_nostat, nf_rst;
+
+  reg [7:0] nf_address = 8'h01;  // Substation data
+  wire [2:0] nf_p3lgth;
+  tri1 diag_scl, diag_sda;
+  wire por;
+
+  wire [5:0] leds;
+
+  // power-on-reset
+  reg rstpo_n = 0;
+  initial begin
+    repeat(3) @(posedge wclk);
+    rstpo_n = 1;
+  end
+
+  assign por = 1'b0;
+
+  //------------------------------------------------
+  diot_urv_top DUT (
+    .clk_25m_i (clk_25m),
+    .por_n_b(por),
+    .button_i(!rstpo_n),
+
+    .dat_i (wb_dat_in),
+    .dat_o (wb_dat_out),
+    .adr_o (wb_adr),
+    .stb_o (wb_stb),
+    .wclk_o(wclk),
+    .we_o  (wb_we),
+    .cyc_o (wb_cyc),
+    .ack_i (wb_ack),
+    .rst_o (wb_rst),
+
+    .rstin_o    (nf_rst),
+    .nostat_o   (nf_nostat),
+    .var3_acc_o (nf_var3_acc),
+    .var3_rdy_i (nf_var3_rdy),
+    .var2_acc_o (nf_var2_acc),
+    .var2_rdy_i (nf_var2_rdy),
+    .var1_acc_o (nf_var1_acc),
+    .var1_rdy_i (nf_var1_rdy),
+    .p3_lgth_o  (nf_p3lgth),
+
+    .diag_scl_b (diag_scl),
+    .diag_sda_b (diag_sda),
+
+    .leds_o(leds));
+
+/*
+  //------------------------------------------------
+  nanofip NF(
+    .c_id_i    (4'hc),  // Constructor field
+    .m_id_i    (4'ha),  // Model field
+    .p3_lgth_i (nf_p3lgth),
+    .rate_i    (fieldrive.speed),
+    .subs_i    (nf_address), // Station address
+    .nostat_i  (nf_nostat),
+
+    .rstin_i  (nf_rst),
+    .rston_o  (),  // Reset output
+    .rstpon_i (rstpo_n),// Power-on-reset
+    .slone_i  (1'b0),   // Disable standalone mode
+    .uclk_i   (clk_40m),   // 40MHz clock
+
+    // Signals accessed by variables 1-3
+    .var1_acc_i(nf_var1_acc),
+    .var2_acc_i(nf_var2_acc),
+    .var3_acc_i(nf_var3_acc),
+    .var1_rdy_o(nf_var1_rdy),
+    .var2_rdy_o(nf_var2_rdy),
+    .var3_rdy_o(nf_var3_rdy),
+
+    // Wishbone
+    .dat_o (wb_dat_in),
+    .dat_i (wb_dat_out),
+    .adr_i (wb_adr),
+    .stb_i (wb_stb),
+    .wclk_i(wclk),
+    .we_i  (wb_we),
+    .cyc_i (wb_cyc),
+    .ack_o (wb_ack),
+    .rst_i (wb_rst),
+
+    // Receiver
+    .fd_rxcdn_i(fieldrive.fd_rxcdn),
+    .fd_rxd_i  (fieldrive.fd_rxd),
+    .fd_txer_i (fieldrive.fd_txer),
+    .fd_wdgn_i (fieldrive.fd_wdgn),
+
+    // Transmitter
+    .fd_rstn_o (fieldrive.fd_rstn),
+    .fd_txck_o (fieldrive.fd_txck),
+    .fd_txd_o  (fieldrive.fd_txd),
+    .fd_txena_o(fieldrive.fd_txena),
+
+    .r_fcser_o (),
+    .r_tler_o  (),
+    .u_cacer_o (),
+    .u_pacer_o (),
+
+    // JTAG interface
+    .jc_tms_o(),
+    .jc_tdi_o(),
+    .jc_tck_o(),
+    .jc_tdo_i(1'b0)
+);
+
+  pentair_fcm2_model sim_FCM2(
+    .clk_i(wclk),
+    .rst_n_i(rstpo_n),
+    .sda_b(diag_sda),
+    .scl_b(diag_scl));
+*/
+endmodule