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DIOT Zynq Ultrascale-based System Board
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DIOT Zynq Ultrascale-based System Board
Issues
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9
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340
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349
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[General] use "_N" suffix for all negative signals (instead of "#")
#7
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Minor
sch-v1
CLOSED
1
updated
Mar 06, 2020
slot7.lvds_0 and slot7.lvds_8 have p/n swapped comparing to FPGA pins functions
#144
· opened
May 11, 2020
by
Grzegorz Daniluk
layout-v1.0
CLOSED
0
updated
Jul 01, 2020
[General] update Copyright to 2019-2020
#10
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Minor
sch-v1
CLOSED
2
updated
Mar 09, 2020
fpga-config: SDIO_PROTECT and SDIO_DETECT should be pulled-up to P3V3 and NOT P1V8
#234
· opened
Apr 06, 2021
by
Grzegorz Daniluk
v2.0
Done
CLOSED
0
updated
Sep 14, 2021
Increase PS DDR to 8 GB
#269
· opened
Apr 13, 2023
by
Grzegorz Daniluk
v3
Done
CLOSED
23
updated
Feb 23, 2024
component designator position
#210
· opened
Jul 03, 2020
by
Paul PERONNARD
layout-v1.0
Done
Minor
CLOSED
0
updated
Aug 31, 2020
updated power budget
#135
· opened
Feb 22, 2020
by
Grzegorz Kasprowicz
CLOSED
3
updated
Apr 02, 2020
[L5] X:116mm Y:39mm sharp corner on otherwise smooth-cornered transceiver lane
#185
· opened
Jul 02, 2020
by
Grzegorz Daniluk
layout-v1.0
Done
Major
CLOSED
0
updated
Aug 28, 2020
power plane pullback distance
#212
· opened
Jul 03, 2020
by
Paul PERONNARD
layout-v1.0
Done
Minor
CLOSED
0
updated
Aug 31, 2020
[L6GND] small cutouts placed around certain pins of IC1 (like SRC_CLK_SEL_R) or P2V5 vias next to C297. What are they for?
#164
· opened
Jul 01, 2020
by
Grzegorz Daniluk
layout-v1.0
Question
CLOSED
1
updated
Jul 14, 2020
[fpga-bank-65-66-67-68] align labels and cleanup
#102
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Minor
sch-v1
CLOSED
1
updated
Mar 18, 2020
MGT connectivity
#281
· opened
Nov 17, 2023
by
Filip Świtakowski
v3
Done
Question
CLOSED
3
updated
Mar 05, 2024
Large vias copied from EDA-03828
#143
· opened
Apr 29, 2020
by
Grzegorz Daniluk
layout-v1.0
CLOSED
0
updated
Jul 01, 2020
[General] PRTR5V0U2X has designator D* in most places except for IC4.
#2
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Major
sch-v1
CLOSED
1
updated
Mar 06, 2020
[DIOT_Controller] "no ERC" directive placed on OVERTHERM signal
#12
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Major
sch-v1
CLOSED
1
updated
Mar 09, 2020
[fpga-ps-mio] SD card series resistors
#77
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Major
sch-v1
CLOSED
1
updated
Mar 16, 2020
[CLK_buffer_DRTIO_CDR] rearrange designators and values of coupling caps for CLK0/CLK1 of IC1
#58
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Minor
sch-v1
CLOSED
1
updated
Mar 11, 2020
[Cpcis_connectors_P1_P2_P3] CPCIS I2C pull-ups
#19
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Major
sch-v1
CLOSED
2
updated
Mar 09, 2020
[i2c_mux] move FMC_I2C, connect it to PS MIO
#65
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Major
sch-v1
CLOSED
4
updated
Mar 12, 2020
SI5341 - reset is powered from 3.3V, should be 3.3VCLK?
#310
· opened
Feb 16, 2024
by
Benjamin Todd
Done
CLOSED
1
updated
Mar 05, 2024
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