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DIOT Zynq Ultrascale-based System Board
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DIOT Zynq Ultrascale-based System Board
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[General] try to equalize via counts from high current power supplies to power planes
#156
· opened
Jul 01, 2020
by
Grzegorz Daniluk
layout-v1.0
Done
Minor
CLOSED
0
updated
Aug 28, 2020
[L1, L14] IC30, IC31 - add more vias on the thermal pads and expose (no soldermask) GND area on bottom layer.
#155
· opened
Jul 01, 2020
by
Grzegorz Daniluk
layout-v1.0
Done
Major
CLOSED
0
updated
Jul 20, 2021
[L1, L14] IC1, IC4 - add more vias on the thermal pads and expose (no soldermask) GND area on bottom layer.
#154
· opened
Jul 01, 2020
by
Grzegorz Daniluk
layout-v1.0
Done
Major
CLOSED
0
updated
Aug 28, 2020
[L1] C308/L12 and around: minor component courtyard overlaps. No real collision between components.
#153
· opened
Jul 01, 2020
by
Grzegorz Daniluk
layout-v1.0
Done
Minor
CLOSED
0
updated
Aug 28, 2020
[General] Clearance rule: do we really need 3 mils?
#152
· opened
Jul 01, 2020
by
Grzegorz Daniluk
layout-v1.0
Done
Question
CLOSED
1
updated
Jul 13, 2020
[General] Reinforce mounting pads such as B3 with via rings.
#151
· opened
Jul 01, 2020
by
Grzegorz Daniluk
layout-v1.0
Done
Major
CLOSED
0
updated
Aug 28, 2020
[General] Mounting pads for FPGA heatsink/fan
#150
· opened
Jul 01, 2020
by
Grzegorz Daniluk
layout-v1.0
Done
Major
CLOSED
1
updated
Aug 28, 2020
[General] Clearance to unplated holes is a bit too tight
#149
· opened
Jul 01, 2020
by
Grzegorz Daniluk
layout-v1.0
Done
Major
CLOSED
1
updated
Sep 08, 2020
[ General] Disable polygon connection (including thermals) to all BGA pads
#148
· opened
Jul 01, 2020
by
Grzegorz Daniluk
layout-v1.0
Done
Major
CLOSED
0
updated
Aug 27, 2020
[General] (X:216mm Y:88.5mm) what's the purpose of that via between backplane P6 connector pins? There is GND pin right next to it.
#147
· opened
Jul 01, 2020
by
Grzegorz Daniluk
layout-v1.0
Done
Question
CLOSED
1
updated
Aug 27, 2020
[General] Impedance of differential pairs not always 100 Ohm, very thin traces (0.075mm)
#146
· opened
Jul 01, 2020
by
Grzegorz Daniluk
layout-v1.0
Done
Major
CLOSED
2
updated
Sep 01, 2020
[General] Clock lanes <n>_PE_CLK_P/N of backplane connector P5 (J31) shall be length matched to provide low-skew clock distribution
#145
· opened
Jul 01, 2020
by
Grzegorz Daniluk
layout-v1.0
Done
Major
CLOSED
3
updated
Aug 27, 2020
[General] Xilinx BGA package delays
#4
· opened
Jan 27, 2020
by
Grzegorz Daniluk
layout-v1.0
Done
Major
CLOSED
10
updated
Sep 03, 2020
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