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DIOT Zynq Ultrascale-based System Board
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DIOT Zynq Ultrascale-based System Board
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[power-supply-3] PG for IC22 and IC32 should be tied to GND or left unconnected if unused
#133
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Major
sch-v1
CLOSED
2
updated
Mar 19, 2020
[power-supply-3] IC32, IC22 feedback dividers
#132
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Major
sch-v1
CLOSED
6
updated
Mar 29, 2020
[power-supply-3] VTT generation for DDR4
#131
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Major
sch-v1
CLOSED
6
updated
Mar 29, 2020
[power-supply-3] IC22 EN input
#130
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Major
sch-v1
CLOSED
4
updated
Mar 18, 2020
[power-supply-2] P3V3 output has a label “5A” while it can deliver 2A max
#128
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Major
sch-v1
CLOSED
16
updated
Mar 30, 2020
[power-supply-2] MGT_1V8 rail capacitors
#127
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Major
sch-v1
CLOSED
2
updated
Mar 18, 2020
[power-supply-1] 1V2 rail caps
#124
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Major
sch-v1
CLOSED
1
updated
Mar 18, 2020
[power-supply-1] R37 sense resistor value
#120
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Major
sch-v1
CLOSED
2
updated
Feb 27, 2020
[power-supply-1] more current for 1V2 (DDR4)
#119
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Major
sch-v1
CLOSED
5
updated
Mar 19, 2020
[power-supply-1] Connect ALERT# to FPGA (if there are still pins available)
#118
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Major
sch-v1
CLOSED
2
updated
Mar 19, 2020
[power-supply-1] Split the use of 5VREG and P5V0_MP
#117
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Major
sch-v1
CLOSED
5
updated
Mar 30, 2020
[power-supply-1] remove no ERC directives from valid signal lines
#116
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Major
sch-v1
CLOSED
5
updated
Apr 02, 2020
[power-supply-1] according to TDA21240 datasheet, max EN pin voltage is 4V. Please change the pull-up
#115
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Major
sch-v1
CLOSED
2
updated
Mar 18, 2020
[fpga-mgts-power] VCCO_63 decoupling
#114
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Major
sch-v1
CLOSED
1
updated
Mar 18, 2020
[ddr4-ps] change pull up/down resistors to 200 Ohms (was 1k) on unused DQS lines
#112
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Major
sch-v1
CLOSED
1
updated
Mar 18, 2020
[ddr4-pl] decoupling caps
#111
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Major
sch-v1
CLOSED
5
updated
Mar 30, 2020
[ddr4-pl] remove DDR4-PL_VREF1, it's never used
#109
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Major
sch-v1
CLOSED
1
updated
Mar 18, 2020
[fpga-bank-64] DDR4 PAR and RST signals
#108
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Major
sch-v1
CLOSED
7
updated
Mar 18, 2020
[fpga-bank-64] DDR4-PL.DQS_N/P0 are connected to FPGA pins not from the same diff pair IO_L16N and IO_L15N)
#107
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Major
sch-v1
CLOSED
2
updated
Mar 18, 2020
[fpga-bank-63] remove "no ERC" flags from signals that are connected
#105
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Major
sch-v1
CLOSED
1
updated
Mar 18, 2020
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