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DIOT Zynq Ultrascale-based System Board
DIOT Zynq Ultrascale-based System Board
Commit f44b41f7 authored by Alén Arias Vázquez's avatar Alén Arias Vázquez 😎
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rename project to fit version 1

parent 0c9301f9
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      Showing with 12 additions and 12 deletions
      gw/projects/diot_sb/src/diot_sb_top.vhd → gw/projects/diot_v2/src/diot_v2_top.vhd
      View file @ f44b41f7
      --==============================================================================
      --! @file diot_sb_top.vhd
      --! @file dios_v2_top.vhd
      --==============================================================================
      --------------------------------------------------------------------------------
      -- --
      -- CERN - dios_sb_top --
      -- CERN - dios_v2 --
      -- --
      --------------------------------------------------------------------------------
      --
      -- unit name: dios_sb_top
      --
      --! @brief top level DIOT system board based in ZynqMP+
      --! @brief top level DIOT system board Version 2 based in ZynqMP+
      --
      --! @author alen.arias.vazquez@cern.ch
      --
      ......@@ -24,9 +24,9 @@ use ieee.std_logic_1164.all;
      use unisim.vcomponents.all;
      --==============================================================================
      --! Entity declaration for diot_sb_top
      --! Entity declaration for dios_v2_top
      --==============================================================================
      entity diot_sb_top is
      entity dios_v2_top is
      port (
      emio_i2c_scl : inout std_logic_vector(0 downto 0);
      emio_i2c_sda : inout std_logic_vector(0 downto 0);
      ......@@ -53,14 +53,14 @@ entity diot_sb_top is
      sfp_txp : out std_logic;
      clk_src_sel_o : out std_logic_vector(1 downto 0)
      );
      end diot_sb_top;
      end dios_v2_top;
      --==============================================================================
      --! Architecture declaration
      --==============================================================================
      architecture structure of diot_sb_top is
      architecture structure of dios_v2_top is
      component diot_sb is
      component diot_v2 is
      port (
      link_status_led : out std_logic_vector(0 downto 0);
      link_sync_led : out std_logic_vector(0 downto 0);
      ......@@ -87,14 +87,14 @@ architecture structure of diot_sb_top is
      sfp_txp : out std_logic;
      clk_src_sel_o : out std_logic_vector(1 downto 0)
      );
      end component diot_sb;
      end component diot_v2;
      --==============================================================================
      --! Architecture begin
      --==============================================================================
      begin
      diot_sb_i: component diot_sb
      diot_v2_i: component diot_v2
      port map (
      emio_i2c_scl(0) => emio_i2c_scl(0),
      emio_i2c_sda(0) => emio_i2c_sda(0),
      ......
      gw/projects/diot_sb/tcl/project_cfg.tcl → gw/projects/diot_v2/tcl/project_cfg.tcl
      View file @ f44b41f7
      # Custom project settings
      set reference_part "xczu7cg-ffvf1517-1-e"
      set project_name "diot_sb"
      set entity_top "diot_sb_top"
      set project_name "diot_v2"
      set entity_top "diot_v2_top"
      # Hardcoded to 8 to work fine in CI set max_threads [get_number_cpus]
      set max_threads 8
      set project_language "VHDL"
      ......
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