Commit e27af1b3 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk

testing: add header_csv

parent c7dab01f
Pipeline #3275 passed with stage
in 29 minutes and 31 seconds
Date,FPGA_T,FMC_T,DDR_T,PowM_T,IRPS1_T,IRPS2_T,PSU1_T,PSU2_T,FANTR_T,IRPS1_IN_V,IRPS1_IN_C,IRPS1_P0V85_V,IRPS1_P0V85_C,IRPS1_P1V8AUX_V,IRPS1_P1V8AUX_C,IRPS1_P1V2_V,IRPS1_P1V2_C,IRPS1_P1V8_V,IRPS1_P1V8_C,IRPS1_LDO_V,IRPS1_LDO_C,IRPS2_IN_V,IRPS2_IN_C,IRPS2_P3V3_V,IRPS2_P3V3_C,IRPS2_1V8_V,IRPS2_1V8_C,IRPS2_0V9_V,IRPS2_0V9_C,IRPS2_1V2_V,IRPS2_1V2_C,
......@@ -36,7 +36,7 @@ def plot_temps(data, period):
sel_cols = ['FPGA_T','FMC_T','DDR_T','PowM_T','IRPS1_T', 'IRPS2_T']
ax[0, 0].set_ylabel('deg C')
ax[0, 0].plot(x[mask], data[mask][sel_cols])
ax[0, 0].legend(data.columns[0:6])
ax[0, 0].legend(sel_cols)
# Not used for now
ax[1, 0].set_facecolor('tab:gray')
......
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