remove buffers from BD, change name signals top levl

afc04cd9 · Alén Arias Vázquez · 6e8d300f · afc04cd9 · afc04cd9 · afc04cd9
Commit afc04cd9 authored May 05, 2022 by Alén Arias Vázquez 😎
5 changed files
--- a/gw/projects/diot_v2/constraints/diot_v2.xdc
+++ b/gw/projects/diot_v2/constraints/diot_v2.xdc
@@ -20,19 +20,19 @@ set_property -dict {PACKAGE_PIN A31 IOSTANDARD LVCMOS18} [get_ports {pwr_cycle_r

 # ------------------------------------------------------------------------------
 # BUS Monitor
-set_property -dict {PACKAGE_PIN J10 IOSTANDARD LVCMOS33} [get_ports {f_rst}]
+set_property -dict {PACKAGE_PIN J10 IOSTANDARD LVCMOS33} [get_ports {f_rst_b}]
 set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS33} [get_ports {p_pres_i_0[0]}]
 set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS33} [get_ports {p_pres_i_0[1]}]

 # ------------------------------------------------------------------------------
 # LEDs:
 # SFP_ACT_LED
-set_property -dict {PACKAGE_PIN J30 IOSTANDARD LVCMOS18} [get_ports {link_status_led[0]}]
+set_property -dict {PACKAGE_PIN J30 IOSTANDARD LVCMOS18} [get_ports {link_status_led}]
 # From USER_LED2 from schematic
 set_property -dict {PACKAGE_PIN AL26 IOSTANDARD LVCMOS18} [get_ports {pl_reset_led}]
 # From USER_LED1 from schematic
-set_property -dict {PACKAGE_PIN AT27 IOSTANDARD LVCMOS18} [get_ports {mdc_clk_led[0]}]
-set_property -dict {PACKAGE_PIN K27 IOSTANDARD LVCMOS18} [get_ports {link_sync_led[0]}]
+set_property -dict {PACKAGE_PIN AT27 IOSTANDARD LVCMOS18} [get_ports {mdc_clk_led}]
+set_property -dict {PACKAGE_PIN K27 IOSTANDARD LVCMOS18} [get_ports {link_sync_led}]

 # ------------------------------------------------------------------------------
 # PSU Alert
@@ -40,18 +40,18 @@ set_property -dict {PACKAGE_PIN AR8 IOSTANDARD LVCMOS18} [get_ports {psu_alert_i

 # ------------------------------------------------------------------------------
 # I2C EMIO
-set_property -dict {PACKAGE_PIN K22 IOSTANDARD LVCMOS18} [get_ports {emio_i2c_scl[0]}]
-set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS18} [get_ports {emio_i2c_sda[0]}]
+set_property -dict {PACKAGE_PIN K22 IOSTANDARD LVCMOS18} [get_ports {emio_scl_b}]
+set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS18} [get_ports {emio_sda_b}]

 # ------------------------------------------------------------------------------
 # I2C wr Flash
-set_property -dict {PACKAGE_PIN AL12 IOSTANDARD LVCMOS18} [get_ports {wrflash_scl[0]}]
-set_property -dict {PACKAGE_PIN AT15 IOSTANDARD LVCMOS18} [get_ports {wrflash_sda[0]}]
+set_property -dict {PACKAGE_PIN AL12 IOSTANDARD LVCMOS18} [get_ports {wrflash_scl_b}]
+set_property -dict {PACKAGE_PIN AT15 IOSTANDARD LVCMOS18} [get_ports {wrflash_sda_b}]

 # ------------------------------------------------------------------------------
 # I2C Backplane
-set_property -dict {IOSTANDARD LVCMOS33 PACKAGE_PIN F15} [get_ports {bckpl_scl}]
-set_property -dict {IOSTANDARD LVCMOS33 PACKAGE_PIN G15} [get_ports {bckpl_sda}]
+set_property -dict {IOSTANDARD LVCMOS33 PACKAGE_PIN F15} [get_ports {bckpl_scl_b}]
+set_property -dict {IOSTANDARD LVCMOS33 PACKAGE_PIN G15} [get_ports {bckpl_sda_b}]

 # ------------------------------------------------------------------------------
 # SFP

--- a/gw/projects/diot_v2/src/constants.vhd
+++ b/gw/projects/diot_v2/src/constants.vhd
--- a/gw/projects/diot_v2/src/diot_v2_top.vhd
+++ b/gw/projects/diot_v2/src/diot_v2_top.vhd
--- a/gw/projects/diot_v2/tcl/create_bd.tcl
+++ b/gw/projects/diot_v2/tcl/create_bd.tcl
--- a/gw/projects/diot_v2/tcl/ps_cfg.tcl
+++ b/gw/projects/diot_v2/tcl/ps_cfg.tcl
@@ -1064,7 +1064,7 @@ MIO} \
    CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {1} \
    CONFIG.PSU__GPIO_EMIO_WIDTH {95} \
    CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {1} \
-    CONFIG.PSU__GPIO_EMIO__PERIPHERAL__IO {95} \
+    CONFIG.PSU__GPIO_EMIO__PERIPHERAL__IO {16} \
    CONFIG.PSU__GPIO_EMIO__WIDTH {[94:0]} \
    CONFIG.PSU__GPU_PP0__POWER__ON {0} \
    CONFIG.PSU__GPU_PP1__POWER__ON {0} \