adding sch v1.0 after CERN reviews and fixes

892076a2 · Grzegorz Daniluk · 5eda1c18 · 892076a2 · 892076a2 · 892076a2
Commit 892076a2 authored Apr 07, 2020 by Grzegorz Daniluk
52 changed files
--- a/hw/DIOT_System_Board.PrjPcb
+++ b/hw/DIOT_System_Board.PrjPcb
--- a/hw/DIOT_System_Board.PrjPcbStructure
+++ b/hw/DIOT_System_Board.PrjPcbStructure
+Record=TopLevelDocument|FileName=DIOT_System_Board.SchDoc
+Record=SheetSymbol|SourceDocument=DIOT_System_Board.SchDoc|Designator=CLK_buffer_DRTIO_CDR|SchDesignator=CLK_buffer_DRTIO_CDR|FileName=CLK_buffer_DRTIO_CDR.SchDoc|SymbolType=Normal|RawFileName=CLK_buffer_DRTIO_CDR.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=DIOT_System_Board.SchDoc|Designator=U_clocks|SchDesignator=U_clocks|FileName=clocks.SchDoc|SymbolType=Normal|RawFileName=clocks.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=DIOT_System_Board.SchDoc|Designator=U_Cpcis_connectors_P1_P2_P3|SchDesignator=U_Cpcis_connectors_P1_P2_P3|FileName=Cpcis_connectors_P1_P2_P3.SchDoc|SymbolType=Normal|RawFileName=Cpcis_connectors_P1_P2_P3.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=DIOT_System_Board.SchDoc|Designator=U_Cpcis_connectors_P4_P5_P6|SchDesignator=U_Cpcis_connectors_P4_P5_P6|FileName=Cpcis_connectors_P4_P5_P6.SchDoc|SymbolType=Normal|RawFileName=Cpcis_connectors_P4_P5_P6.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=DIOT_System_Board.SchDoc|Designator=U_ddr4-pl|SchDesignator=U_ddr4-pl|FileName=ddr4-pl.SchDoc|SymbolType=Normal|RawFileName=ddr4-pl.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=DIOT_System_Board.SchDoc|Designator=U_ddr4-ps|SchDesignator=U_ddr4-ps|FileName=ddr4-ps.SchDoc|SymbolType=Normal|RawFileName=ddr4-ps.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=DIOT_System_Board.SchDoc|Designator=U_fan-mon|SchDesignator=U_fan-mon|FileName=fan-mon.SchDoc|SymbolType=Normal|RawFileName=fan-mon.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=DIOT_System_Board.SchDoc|Designator=U_flash|SchDesignator=U_flash|FileName=flash.SchDoc|SymbolType=Normal|RawFileName=flash.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=DIOT_System_Board.SchDoc|Designator=U_fmc-connector|SchDesignator=U_fmc-connector|FileName=fmc-connector.SchDoc|SymbolType=Normal|RawFileName=fmc-connector.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=DIOT_System_Board.SchDoc|Designator=U_fpga-bank-27-28|SchDesignator=U_fpga-bank-27-28|FileName=fpga-bank-27-28.SchDoc|SymbolType=Normal|RawFileName=fpga-bank-27-28.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=DIOT_System_Board.SchDoc|Designator=U_fpga-bank-63|SchDesignator=U_fpga-bank-63|FileName=fpga-bank-63.SchDoc|SymbolType=Normal|RawFileName=fpga-bank-63.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=DIOT_System_Board.SchDoc|Designator=U_fpga-bank-64|SchDesignator=U_fpga-bank-64|FileName=fpga-bank-64.SchDoc|SymbolType=Normal|RawFileName=fpga-bank-64.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=DIOT_System_Board.SchDoc|Designator=U_fpga-bank-65-66-67-68|SchDesignator=U_fpga-bank-65-66-67-68|FileName=fpga-bank-65-66-67-68.SchDoc|SymbolType=Normal|RawFileName=fpga-bank-65-66-67-68.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=DIOT_System_Board.SchDoc|Designator=U_fpga-bank-87-88|SchDesignator=U_fpga-bank-87-88|FileName=fpga-bank-87-88.SchDoc|SymbolType=Normal|RawFileName=fpga-bank-87-88.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=DIOT_System_Board.SchDoc|Designator=U_fpga-config|SchDesignator=U_fpga-config|FileName=fpga-config.SchDoc|SymbolType=Normal|RawFileName=fpga-config.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=DIOT_System_Board.SchDoc|Designator=U_fpga-mgts-power|SchDesignator=U_fpga-mgts-power|FileName=fpga-mgts-power.SchDoc|SymbolType=Normal|RawFileName=fpga-mgts-power.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=DIOT_System_Board.SchDoc|Designator=U_fpga-pl-mgts|SchDesignator=U_fpga-pl-mgts|FileName=fpga-pl-mgts.SchDoc|SymbolType=Normal|RawFileName=fpga-pl-mgts.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=DIOT_System_Board.SchDoc|Designator=U_fpga-power|SchDesignator=U_fpga-power|FileName=fpga-power.SchDoc|SymbolType=Normal|RawFileName=fpga-power.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=DIOT_System_Board.SchDoc|Designator=U_fpga-ps-ddr4|SchDesignator=U_fpga-ps-ddr4|FileName=fpga-ps-ddr4.SchDoc|SymbolType=Normal|RawFileName=fpga-ps-ddr4.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=DIOT_System_Board.SchDoc|Designator=U_fpga-ps-mgts|SchDesignator=U_fpga-ps-mgts|FileName=fpga-ps-mgts.SchDoc|SymbolType=Normal|RawFileName=fpga-ps-mgts.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=DIOT_System_Board.SchDoc|Designator=U_fpga-ps-mio|SchDesignator=U_fpga-ps-mio|FileName=fpga-ps-mio.SchDoc|SymbolType=Normal|RawFileName=fpga-ps-mio.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=DIOT_System_Board.SchDoc|Designator=U_i2c_mux|SchDesignator=U_i2c_mux|FileName=i2c_mux.SchDoc|SymbolType=Normal|RawFileName=i2c_mux.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=DIOT_System_Board.SchDoc|Designator=U_power-supply-1|SchDesignator=U_power-supply-1|FileName=power-supply-1.SchDoc|SymbolType=Normal|RawFileName=power-supply-1.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=DIOT_System_Board.SchDoc|Designator=U_power-supply-2|SchDesignator=U_power-supply-2|FileName=power-supply-2.SchDoc|SymbolType=Normal|RawFileName=power-supply-2.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=DIOT_System_Board.SchDoc|Designator=U_power-supply-3|SchDesignator=U_power-supply-3|FileName=power-supply-3.SchDoc|SymbolType=Normal|RawFileName=power-supply-3.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=DIOT_System_Board.SchDoc|Designator=U_sfp+|SchDesignator=U_sfp+|FileName=sfp+.SchDoc|SymbolType=Normal|RawFileName=sfp+.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=DIOT_System_Board.SchDoc|Designator=U_user_interface|SchDesignator=U_user_interface|FileName=user_interface.SchDoc|SymbolType=Normal|RawFileName=user_interface.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=DIOT_System_Board.SchDoc|Designator=U_WR-clocks|SchDesignator=U_WR-clocks|FileName=WR-clocks.SchDoc|SymbolType=Normal|RawFileName=WR-clocks.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
--- a/hw/sch/CLK_buffer_DRTIO_CDR.Harness
+++ b/hw/sch/CLK_buffer_DRTIO_CDR.Harness
+CDR_PLL_CTRL=Main_DCXO_SDA,Main_DCXO_SCL,Main_DCXO_OE,Helper_DCXO_OE,Helper_DCXO_SDA,Helper_DCXO_SCL
+CLK_DIFF=CLK_P,CLK_N
+DRTIO_CLK=DRTIO_MAIN_P,DRTIO_MAIN_N,DRTIO_HELPER_P,DRTIO_HELPER_N
+PE_CLK=1_PE_CLK_P,1_PE_CLK_N,2_PE_CLK_P,2_PE_CLK_N,3_PE_CLK_P,3_PE_CLK_N,4_PE_CLK_P,4_PE_CLK_N,5_PE_CLK_P,5_PE_CLK_N,6_PE_CLK_P,6_PE_CLK_N,7_PE_CLK_P,7_PE_CLK_N,8_PE_CLK_P,8_PE_CLK_N
--- a/hw/sch/CLK_buffer_DRTIO_CDR.SchDoc
+++ b/hw/sch/CLK_buffer_DRTIO_CDR.SchDoc
--- a/hw/sch/Cpcis_connectors_P1_P2_P3.Harness
+++ b/hw/sch/Cpcis_connectors_P1_P2_P3.Harness
+CPCIS_BUS_CTRL=PS_ON_N,RST_N,PRST_N,PWRBTN_N,PWR_FAIL_N
+I2C=SDA,SCL
+MGT=MGT_Tx_P,MGT_Tx_N,MGT_Rx_P,MGT_Rx_N
+MON-bus=M_SCL,M_SDA,P_IO0,P_IO1,P_IO2,P_PRES0,P_PRES1,F_RST,P_RST,F_IO0,F_IO1
--- a/hw/sch/Cpcis_connectors_P1_P2_P3.SchDoc
+++ b/hw/sch/Cpcis_connectors_P1_P2_P3.SchDoc
--- a/hw/sch/Cpcis_connectors_P4_P5_P6.Harness
+++ b/hw/sch/Cpcis_connectors_P4_P5_P6.Harness
+MGT=MGT_Tx_P,MGT_Tx_N,MGT_Rx_P,MGT_Rx_N
+PE_CLK=1_PE_CLK_P,1_PE_CLK_N,2_PE_CLK_P,2_PE_CLK_N,3_PE_CLK_P,3_PE_CLK_N,4_PE_CLK_P,4_PE_CLK_N,5_PE_CLK_P,5_PE_CLK_N,6_PE_CLK_P,6_PE_CLK_N,7_PE_CLK_P,7_PE_CLK_N,8_PE_CLK_P,8_PE_CLK_N
+SERVMOD_N=1_SERVMOD_N,2_SERVMOD_N,3_SERVMOD_N,4_SERVMOD_N,5_SERVMOD_N,6_SERVMOD_N,7_SERVMOD_N,8_SERVMOD_N
--- a/hw/sch/Cpcis_connectors_P4_P5_P6.SchDoc
+++ b/hw/sch/Cpcis_connectors_P4_P5_P6.SchDoc
--- a/hw/sch/DIOT_System_Board.SchDoc
+++ b/hw/sch/DIOT_System_Board.SchDoc
--- a/hw/sch/WR-clocks.Harness
+++ b/hw/sch/WR-clocks.Harness
+CLK_DIFF=CLK_P,CLK_N
+WR_DAC_H=SCLK,DIN,SYNC1,SYNC2
--- a/hw/sch/WR-clocks.SchDoc
+++ b/hw/sch/WR-clocks.SchDoc
--- a/hw/sch/clocks.Harness
+++ b/hw/sch/clocks.Harness
+CLK_DIFF=CLK_P,CLK_N
+I2C=SDA,SCL
+MGT_CLKREF_H=CLK_P[3..0],CLK_N[3..0]
--- a/hw/sch/clocks.SchDoc
+++ b/hw/sch/clocks.SchDoc
--- a/hw/sch/ddr4-pl.Harness
+++ b/hw/sch/ddr4-pl.Harness
+DDR4-PL_H=DQ[15..0],DM[1..0],DQS_P[1..0],DQS_N[1..0],CK_P,CK_N,CKE,ACT_N,PAR,CS_N,ODT,BA[1..0],BG0,A[13..0],WE_N,CAS_N,RAS_N
--- a/hw/sch/ddr4-pl.SchDoc
+++ b/hw/sch/ddr4-pl.SchDoc
--- a/hw/sch/ddr4-ps.Harness
+++ b/hw/sch/ddr4-ps.Harness
+DDR4-PS_H=DQ[71..0],DM[8..0],DQS_P[8..0],DQS_N[8..0],A[16..0],CK_P,CK_N,CKE,RST_N,ACT_N,PAR,CS_N,ODT,BA[1..0],BG0,ALERT_N
--- a/hw/sch/ddr4-ps.SchDoc
+++ b/hw/sch/ddr4-ps.SchDoc
--- a/hw/sch/fan-mon.Harness
+++ b/hw/sch/fan-mon.Harness
+I2C=SDA,SCL
--- a/hw/sch/fan-mon.SchDoc
+++ b/hw/sch/fan-mon.SchDoc
--- a/hw/sch/flash.Harness
+++ b/hw/sch/flash.Harness
+I2C_H=SDA,SCL
+PS-EMMC_H=D[7..0],CMD,CLK
+PSI-QSPI_H=LWR_DQ[3..0],LWR_CLK,LWR_CS_N,UWR_DQ[3..0],UWR_CLK,UWR_CS_N
--- a/hw/sch/flash.SchDoc
+++ b/hw/sch/flash.SchDoc
--- a/hw/sch/fmc-connector.Harness
+++ b/hw/sch/fmc-connector.Harness
+FMC_JTAG_H=TCK,TDI,TDO,TMS,TRST
+FMC_L=LA_P[33..0],LA_N[33..0],CLK_M2C_P[1..0],CLK_M2C_N[1..0],VREFA_M2C
+FMC_MGT=GBTCLK_M2C_P[1..0],GBTCLK_M2C_N[1..0],DP_C2M_P[7..0],DP_C2M_N[7..0],DP_M2C_P[7..0],DP_M2C_N[7..0]
+I2C=SDA,SCL
--- a/hw/sch/fmc-connector.SchDoc
+++ b/hw/sch/fmc-connector.SchDoc
--- a/hw/sch/fpga-bank-27-28.Harness
+++ b/hw/sch/fpga-bank-27-28.Harness
+CDR_PLL_CTRL=Helper_DCXO_SCL,Helper_DCXO_SDA,Helper_DCXO_OE,Main_DCXO_OE,Main_DCXO_SCL,Main_DCXO_SDA
+CLK_DIFF=CLK_N,CLK_P
+FMC_L=LA_P[33..0],LA_N[33..0],CLK_M2C_P[1..0],CLK_M2C_N[1..0],VREFA_M2C
--- a/hw/sch/fpga-bank-27-28.SchDoc
+++ b/hw/sch/fpga-bank-27-28.SchDoc
--- a/hw/sch/fpga-bank-63.Harness
+++ b/hw/sch/fpga-bank-63.Harness
+CLK_DIFF=CLK_N,CLK_P
+DDR4-PL_H=DQ[15..0],DM[1..0],DQS_P[1..0],DQS_N[1..0],CK_P,CK_N,CKE,ACT_N,PAR,CS_N,ODT,BA[1..0],BG0,A[13..0],WE_N,CAS_N,RAS_N
--- a/hw/sch/fpga-bank-63.SchDoc
+++ b/hw/sch/fpga-bank-63.SchDoc
--- a/hw/sch/fpga-bank-64.SchDoc
+++ b/hw/sch/fpga-bank-64.SchDoc
--- a/hw/sch/fpga-bank-65-66-67-68.Harness
+++ b/hw/sch/fpga-bank-65-66-67-68.Harness
+SLOT=LVDS_0_P,LVDS_0_N,LVDS_1_P,LVDS_1_N,LVDS_2_P,LVDS_2_N,LVDS_3_P,LVDS_3_N,LVDS_4_P,LVDS_4_N,LVDS_5_P,LVDS_5_N,LVDS_6_P,LVDS_6_N,LVDS_7_P,LVDS_7_N,LVDS_8_P,LVDS_8_N,LVDS_9_P,LVDS_9_N,LVDS_10_P,LVDS_10_N,LVDS_11_P,LVDS_11_N,LVDS_12_P,LVDS_12_N,LVDS_13_P,LVDS_13_N,LVDS_14_P,LVDS_14_N,LVDS_15_P,LVDS_15_N
--- a/hw/sch/fpga-bank-65-66-67-68.SchDoc
+++ b/hw/sch/fpga-bank-65-66-67-68.SchDoc
--- a/hw/sch/fpga-bank-87-88.Harness
+++ b/hw/sch/fpga-bank-87-88.Harness
+CLK_DIFF=CLK_N,CLK_P
+CPCIS_BUS_CTRL=PS_ON_N,RST_N,PRST_N,PWRBTN_N,PWR_FAIL_N
+DRTIO_CLK=DRTIO_MAIN_N,DRTIO_MAIN_P,DRTIO_HELPER_N,DRTIO_HELPER_P
+I2C=SCL,SDA
+MON-bus=F_IO1,F_IO0,P_RST,F_RST,P_PRES1,P_PRES0,P_IO2,P_IO1,P_IO0,M_SDA,M_SCL
+SERVMOD_N=1_SERVMOD_N,2_SERVMOD_N,3_SERVMOD_N,4_SERVMOD_N,5_SERVMOD_N,6_SERVMOD_N,7_SERVMOD_N,8_SERVMOD_N
--- a/hw/sch/fpga-bank-87-88.SchDoc
+++ b/hw/sch/fpga-bank-87-88.SchDoc
--- a/hw/sch/fpga-config.SchDoc
+++ b/hw/sch/fpga-config.SchDoc
--- a/hw/sch/fpga-mgts-power.SchDoc
+++ b/hw/sch/fpga-mgts-power.SchDoc
--- a/hw/sch/fpga-pl-mgts.Harness
+++ b/hw/sch/fpga-pl-mgts.Harness
+CLK_DIFF=CLK_N,CLK_P
+FMC_MGT=GBTCLK_M2C_P[1..0],GBTCLK_M2C_N[1..0],DP_C2M_P[7..0],DP_C2M_N[7..0],DP_M2C_P[7..0],DP_M2C_N[7..0]
+MGT=MGT_Tx_P,MGT_Tx_N,MGT_Rx_P,MGT_Rx_N
--- a/hw/sch/fpga-pl-mgts.SchDoc
+++ b/hw/sch/fpga-pl-mgts.SchDoc
--- a/hw/sch/fpga-power.SchDoc
+++ b/hw/sch/fpga-power.SchDoc
--- a/hw/sch/fpga-ps-ddr4.SchDoc
+++ b/hw/sch/fpga-ps-ddr4.SchDoc
--- a/hw/sch/fpga-ps-mgts.SchDoc
+++ b/hw/sch/fpga-ps-mgts.SchDoc
--- a/hw/sch/fpga-ps-mio.Harness
+++ b/hw/sch/fpga-ps-mio.Harness
+I2C=SDA,SCL
--- a/hw/sch/fpga-ps-mio.SchDoc
+++ b/hw/sch/fpga-ps-mio.SchDoc
--- a/hw/sch/i2c_mux.Harness
+++ b/hw/sch/i2c_mux.Harness
+I2C=SDA,SCL
--- a/hw/sch/i2c_mux.SchDoc
+++ b/hw/sch/i2c_mux.SchDoc
--- a/hw/sch/power-supply-1.Harness
+++ b/hw/sch/power-supply-1.Harness
+I2C=SCL,SDA
--- a/hw/sch/power-supply-1.SchDoc
+++ b/hw/sch/power-supply-1.SchDoc
--- a/hw/sch/power-supply-2.Harness
+++ b/hw/sch/power-supply-2.Harness
+I2C=SCL,SDA
--- a/hw/sch/power-supply-2.SchDoc
+++ b/hw/sch/power-supply-2.SchDoc
--- a/hw/sch/power-supply-3.SchDoc
+++ b/hw/sch/power-supply-3.SchDoc
--- a/hw/sch/pxie_connector.Harness
+++ b/hw/sch/pxie_connector.Harness
+PXIe_H=TRIG[7..0],GA[4..0],STAR,LBL6,LBR6,CLK10,DSTARA_P,DSTARA_N,DSTARB_P,DSTARB_N,DSTARC_P,DSTARC_N,CLK100_P,CLK100_N,SYNC100_P,SYNC100_N,PERSTn,MPWRGD
+PXIe_MGT_H=TX_P[3..0],TX_N[3..0],RX_P[3..0],RX_N[3..0],REFCLK_P,REFCLK_N
--- a/hw/sch/sfp+.Harness
+++ b/hw/sch/sfp+.Harness
+MGT=MGT_Rx_N,MGT_Rx_P,MGT_Tx_N,MGT_Tx_P
--- a/hw/sch/sfp+.SchDoc
+++ b/hw/sch/sfp+.SchDoc
--- a/hw/sch/user_interface.SchDoc
+++ b/hw/sch/user_interface.SchDoc