Commit 849d80e0 authored by Alén Arias Vázquez's avatar Alén Arias Vázquez 😎

added RST SYNC

parent ee881dde
Pipeline #4052 passed with stages
in 147 minutes and 48 seconds
...@@ -49,7 +49,7 @@ module dna_reader # ( ...@@ -49,7 +49,7 @@ module dna_reader # (
wire s_data; wire s_data;
//! FSM //! FSM
always @(posedge clk_i, negedge rst_n_i) always @(posedge clk_i)
begin : p_fsm begin : p_fsm
if(! rst_n_i) begin if(! rst_n_i) begin
s_read <= 1'b0; s_read <= 1'b0;
...@@ -108,7 +108,7 @@ module dna_reader # ( ...@@ -108,7 +108,7 @@ module dna_reader # (
end : p_fsm end : p_fsm
//! Shift Register //! Shift Register
always @(posedge clk_i, negedge rst_n_i) always @(posedge clk_i)
begin : p_shift begin : p_shift
if (! rst_n_i) if (! rst_n_i)
s_dna <= 'h0; s_dna <= 'h0;
......
...@@ -123,7 +123,7 @@ module fpga_device # ( ...@@ -123,7 +123,7 @@ module fpga_device # (
//-------------------------------------------------------------------------- //--------------------------------------------------------------------------
//! ARREADY LOGIC & ARADDR Latch //! ARREADY LOGIC & ARADDR Latch
always @(posedge S_AXI_ACLK, negedge S_AXI_ARESETN) always @(posedge S_AXI_ACLK)
begin : p_arready begin : p_arready
if (! S_AXI_ARESETN) begin if (! S_AXI_ARESETN) begin
s_araddr <= 'h0; s_araddr <= 'h0;
...@@ -144,7 +144,7 @@ module fpga_device # ( ...@@ -144,7 +144,7 @@ module fpga_device # (
assign S_AXI_ARREADY = s_arready; assign S_AXI_ARREADY = s_arready;
//! RVALID //! RVALID
always @(posedge S_AXI_ACLK, negedge S_AXI_ARESETN) always @(posedge S_AXI_ACLK)
begin : p_rvalid begin : p_rvalid
if (! S_AXI_ARESETN) if (! S_AXI_ARESETN)
s_rvalid <= 1'b0; s_rvalid <= 1'b0;
...@@ -161,7 +161,7 @@ module fpga_device # ( ...@@ -161,7 +161,7 @@ module fpga_device # (
assign s_REN = ~(s_rvalid) & s_arready & S_AXI_ARVALID; assign s_REN = ~(s_rvalid) & s_arready & S_AXI_ARVALID;
//! Register Access //! Register Access
always @(posedge S_AXI_ACLK, negedge S_AXI_ARESETN) always @(posedge S_AXI_ACLK)
begin : p_read begin : p_read
if (! S_AXI_ARESETN) if (! S_AXI_ARESETN)
s_RDATA <= 'h0; s_RDATA <= 'h0;
......
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