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DIOT Zynq Ultrascale-based System Board
DIOT Zynq Ultrascale-based System Board
Commit 78752934 authored by Maciej Lipinski's avatar Maciej Lipinski
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Updated declaration of added sources. 

Now the sources are decalred with the full path. This allows using
a single loop in the build_project.tcl to add sources from different
projects. This is used when basing a new project on a base project
(e.g. diot_fsi project calls scripts and uses sources of the base
diot_v2 project)
parent 9ea27130
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Showing with 19 additions and 11 deletions
gw/build_project.tcl
View file @ 78752934
......@@ -49,7 +49,7 @@ if [ info exist ::user_list(SRC_VHDL) ] {
set vhdl_src [ lindex ${list_vhdl} ${i} ]
set vhdl_lib [ lindex ${list_lib} ${i} ]
write_msg "INFO: Adding VHLD file ${vhdl_src}" "1"
read_vhdl -library ${vhdl_lib} ${target_path}/src/${vhdl_src}
read_vhdl -library ${vhdl_lib} ${vhdl_src}
}
}
......@@ -62,7 +62,7 @@ if [ info exist ::user_list(SRC_VHDL08) ] {
set vhdl_src [ lindex ${list_vhdl} ${i} ]
set vhdl_lib [ lindex ${list_lib} ${i} ]
write_msg "INFO: Adding VHLD 2008 file ${vhdl_src}" "1"
read_vhdl -library ${vhdl_lib} -2008 ${target_path}/src/${vhdl_src}
read_vhdl -library ${vhdl_lib} -2008 ${vhdl_src}
}
}
......@@ -74,10 +74,10 @@ if [ info exist ::user_list(SRC_VERILOG) ] {
set ver_src [ lindex ${list_ver} ${i} ]
if { [ enable_sv_compilation ${ver_src} ] == 1 } {
write_msg "INFO: Adding SystemVerilog file ${ver_src}" "1"
read_verilog -library ${lib_default} -sv ${target_path}/src/${ver_src}
read_verilog -library ${lib_default} -sv ${ver_src}
} else {
write_msg "INFO: Adding Verilog file ${ver_src}" "1"
read_verilog -library ${lib_default} ${target_path}/src/${ver_src}
read_verilog -library ${lib_default} ${ver_src}
}
}
}
......@@ -89,7 +89,7 @@ if [ info exist ::user_list(CONSTRAINT) ] {
for { set i 0 } { $i < ${list_names_max_i} } { incr i } {
set file_xdc [ lindex ${list_xdc} ${i} ]
write_msg "INFO: Adding XDC file ${file_xdc}" "1"
read_xdc ${target_path}/constraints/${file_xdc}
read_xdc ${file_xdc}
}
}
......
gw/projects/diot_v1/tcl/project_cfg.tcl
View file @ 78752934
......@@ -12,11 +12,15 @@ set_user_property "default_lib" "xil_defaultlib"
set_user_property "enable_vhdl_2008" "1"
set_user_property "xpm_libraries" "XPM_CDC XPM_FIFO XPM_MEMORY"
set path [pwd]
set path_hdl $path/projects/$project_name/src
set path_xdc $path/projects/$project_name/constraints
# Top Level
add_vhdl_src ${lib_default} ../src/${entity_top}.vhd
add_vhdl_src ${lib_default} $path_hdl/${entity_top}.vhd
# Vhdl Src
add_vhdl_src ${lib_default} ../src/constants.vhd
add_vhdl_src ${lib_default} $path_hdl/constants.vhd
# Add Constraints
add_constraint diot_v1.xdc
add_constraint $path_xdc/diot_v1.xdc
gw/projects/diot_v2/tcl/project_cfg.tcl
View file @ 78752934
......@@ -12,11 +12,15 @@ set_user_property "default_lib" "xil_defaultlib"
set_user_property "enable_vhdl_2008" "1"
set_user_property "xpm_libraries" "XPM_CDC XPM_FIFO XPM_MEMORY"
set path [pwd]
set path_hdl $path/projects/$project_name/src
set path_xdc $path/projects/$project_name/constraints
# Top Level
add_vhdl_src ${lib_default} ../src/${entity_top}.vhd
add_vhdl_src ${lib_default} $path_hdl/${entity_top}.vhd
# Vhdl Src
add_vhdl_src ${lib_default} ../src/constants.vhd
add_vhdl_src ${lib_default} $path_hdl/constants.vhd
# Add Constraints
add_constraint diot_v2.xdc
add_constraint $path_xdc/diot_v2.xdc
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