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DIOT Zynq Ultrascale-based System Board
DIOT Zynq Ultrascale-based System Board
Commit 5a0338d6 authored by Adam Wujek's avatar Adam Wujek
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sw/Makefile: pick gateware file based on SB_VER 

Signed-off-by: 's avatarAdam Wujek <dev_public@wujek.eu>
parent e6b0d163
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sw/Makefile
View file @ 5a0338d6
......@@ -43,7 +43,7 @@ endif
DTC_BIN=artifacts/dtc
GW_XSA=gw/diot_sb_golden.xsa
GW_XSA=gw/hw_v$(SB_VER)/diot_sb_golden_hw_v$(SB_VER).xsa
export CROSS_COMPILE=aarch64-none-elf-
export ARCH=aarch64
CROSS_COMPILE_MICROBLAZE=mb-
......
sw/gw/diot_sb_golden.xsa deleted 120000 → 0
View file @ e6b0d163
../gw_all/diot_sb_golden_2021_10_22_3.xsa
\ No newline at end of file
sw/gw/hw_v1/diot_sb_golden_hw_v1.xsa 0 → 120000
View file @ 5a0338d6
../../gw_all/diot_sb_golden_2021_10_22_3.xsa
\ No newline at end of file
sw/gw/hw_v2/diot_sb_golden_hw_v2.xsa 0 → 120000
View file @ 5a0338d6
../../gw_all/diot_sb_hw_v2_golden_2021_12_16.xsa
\ No newline at end of file
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