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DIOT Zynq Ultrascale-based System Board
Commits
50770cf2
Commit
50770cf2
authored
Jul 28, 2022
by
Adrian Byszuk
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Plain Diff
GW: add Chip2Chip/Aurora subsystem to BD
parent
a23c7dbd
Pipeline
#3842
passed with stages
in 150 minutes and 4 seconds
Changes
4
Pipelines
1
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4 changed files
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1957 additions
and
212 deletions
+1957
-212
diot_v2.xdc
gw/projects/diot_v2/constraints/diot_v2.xdc
+15
-2
diot_v2_top.vhd
gw/projects/diot_v2/src/diot_v2_top.vhd
+121
-47
create_bd.tcl
gw/projects/diot_v2/tcl/create_bd.tcl
+1771
-104
ps_cfg.tcl
gw/projects/diot_v2/tcl/ps_cfg.tcl
+50
-59
No files found.
gw/projects/diot_v2/constraints/diot_v2.xdc
View file @
50770cf2
...
...
@@ -5,9 +5,11 @@
# ##############################################################################
# ------------------------------------------------------------------------------
# GT RE
G
CLK: 125 MHz
# GT RE
F
CLK: 125 MHz
set_property PACKAGE_PIN AH10 [get_ports {gtrefclk_in_clk_p}]
create_clock -period 8.000 -name gt_ref_clk -waveform {0.000 4.000} [get_ports {gtrefclk_in_clk_p}]
set_property PACKAGE_PIN AA12 [get_ports {aurora_refclk_p}]
create_clock -period 8.000 -name aurora_ref_clk [get_ports {aurora_refclk_p}]
# ------------------------------------------------------------------------------
# Clock Selector
...
...
@@ -62,7 +64,7 @@ set_property PACKAGE_PIN AJ8 [get_ports sfp_txp]
set_property PACKAGE_PIN AJ7 [get_ports sfp_txn]
# ------------------------------------------------------------------------------
# Backpla
in
# Backpla
ne
set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {bckpl_servmod_b[0]}]
set_property -dict {PACKAGE_PIN A13 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {bckpl_servmod_b[1]}]
set_property -dict {PACKAGE_PIN B13 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {bckpl_servmod_b[2]}]
...
...
@@ -72,3 +74,14 @@ set_property -dict {PACKAGE_PIN C13 IOSTANDARD LVCMOS33 PULLUP true} [get_ports
set_property -dict {PACKAGE_PIN D14 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {bckpl_servmod_b[6]}]
set_property -dict {PACKAGE_PIN A15 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {bckpl_servmod_b[7]}]
set_property -dict {PACKAGE_PIN H11 IOSTANDARD LVCMOS33} [get_ports {bckpl_rst_n_o}]
# ------------------------------------------------------------------------------
# Aurora GTX pins are defined in the block desing IP GUI
# Overwriting them here will only generate placement conflicts
# ------------------------------------------------------------------------------
# Timing ignore for quasi-static status signals
set_false_path -from [get_pins diot_v2_i/chip2chip_subsystem/link_*/aurora/*/*/*/CHANNEL_UP_reg/C] \
-to [get_pins {diot_v2_i/chip2chip_subsystem/c2c_link_ctrl/*/*/rd_data_reg[0]/D}]
set_false_path -from [get_pins diot_v2_i/chip2chip_subsystem/link_*/aurora/*/*/*/CHANNEL_HARD_ERR_reg/C] \
-to [get_pins {diot_v2_i/chip2chip_subsystem/c2c_link_ctrl/*/*/rd_data_reg[1]/D}]
gw/projects/diot_v2/src/diot_v2_top.vhd
View file @
50770cf2
...
...
@@ -51,7 +51,13 @@ entity diot_v2_top is
emio_scl_b
:
inout
std_logic
;
emio_sda_b
:
inout
std_logic
;
wrflash_scl_b
:
inout
std_logic
;
wrflash_sda_b
:
inout
std_logic
wrflash_sda_b
:
inout
std_logic
;
aurora_refclk_p
:
in
std_logic
;
aurora_refclk_n
:
in
std_logic
;
aurora_rx_p
:
in
std_logic_vector
(
7
downto
0
);
aurora_rx_n
:
in
std_logic_vector
(
7
downto
0
);
aurora_tx_p
:
out
std_logic_vector
(
7
downto
0
);
aurora_tx_n
:
out
std_logic_vector
(
7
downto
0
)
);
end
diot_v2_top
;
...
...
@@ -62,60 +68,94 @@ architecture structure of diot_v2_top is
component
diot_v2
is
port
(
f_rst_i
:
in
std_logic
;
f_rst_o
:
out
std_logic
;
f_rst_t
:
out
std_logic
;
psu_alert_i
:
in
std_logic
;
p_pres_i_0
:
in
std_logic_vector
(
1
downto
0
);
pwr_cycle_req_o_0
:
out
std_logic
;
clk_src_sel_o
:
out
std_logic_vector
(
1
downto
0
);
gtrefclk_in_clk_p
:
in
std_logic
;
gtrefclk_in_clk_n
:
in
std_logic
;
pl_reset_led
:
out
std_logic
;
link_status_led
:
out
std_logic
;
link_sync_led
:
out
std_logic
;
mdc_clk_led
:
out
std_logic
;
tx_disable_o
:
out
std_logic
;
sfp_rxp
:
in
std_logic
;
sfp_rxn
:
in
std_logic
;
sfp_txp
:
out
std_logic
;
sfp_txn
:
out
std_logic
;
bckpl_rst_n_o
:
out
std_logic
;
bckpl_servmod_i
:
in
std_logic_vector
(
7
downto
0
);
bckpl_servmod_o
:
out
std_logic_vector
(
7
downto
0
);
bckpl_servmod_t
:
out
std_logic_vector
(
7
downto
0
);
i2c_bckpl_scl_i
:
in
std_logic
;
i2c_bckpl_scl_o
:
out
std_logic
;
i2c_bckpl_scl_t
:
out
std_logic
;
i2c_bckpl_sda_i
:
in
std_logic
;
i2c_bckpl_sda_o
:
out
std_logic
;
i2c_bckpl_sda_t
:
out
std_logic
;
i2c_emio_scl_i
:
in
std_logic
;
i2c_emio_scl_o
:
out
std_logic
;
i2c_emio_scl_t
:
out
std_logic
;
i2c_emio_sda_i
:
in
std_logic
;
i2c_emio_sda_o
:
out
std_logic
;
i2c_emio_sda_t
:
out
std_logic
;
i2c_wrflash_scl_i
:
in
std_logic
;
i2c_wrflash_scl_o
:
out
std_logic
;
i2c_wrflash_scl_t
:
out
std_logic
;
i2c_wrflash_sda_i
:
in
std_logic
;
i2c_wrflash_sda_o
:
out
std_logic
;
i2c_wrflash_sda_t
:
out
std_logic
f_rst_i
:
in
std_logic
;
f_rst_o
:
out
std_logic
;
f_rst_t
:
out
std_logic
;
psu_alert_i
:
in
std_logic
;
p_pres_i_0
:
in
std_logic_vector
(
1
downto
0
);
pwr_cycle_req_o_0
:
out
std_logic
;
clk_src_sel_o
:
out
std_logic_vector
(
1
downto
0
);
gtrefclk_in_clk_p
:
in
std_logic
;
gtrefclk_in_clk_n
:
in
std_logic
;
pl_reset_led
:
out
std_logic
;
link_status_led
:
out
std_logic
;
link_sync_led
:
out
std_logic
;
mdc_clk_led
:
out
std_logic
;
tx_disable_o
:
out
std_logic
;
sfp_rxp
:
in
std_logic
;
sfp_rxn
:
in
std_logic
;
sfp_txp
:
out
std_logic
;
sfp_txn
:
out
std_logic
;
bckpl_rst_n_o
:
out
std_logic
;
bckpl_servmod_i
:
in
std_logic_vector
(
7
downto
0
);
bckpl_servmod_o
:
out
std_logic_vector
(
7
downto
0
);
bckpl_servmod_t
:
out
std_logic_vector
(
7
downto
0
);
i2c_bckpl_scl_i
:
in
std_logic
;
i2c_bckpl_scl_o
:
out
std_logic
;
i2c_bckpl_scl_t
:
out
std_logic
;
i2c_bckpl_sda_i
:
in
std_logic
;
i2c_bckpl_sda_o
:
out
std_logic
;
i2c_bckpl_sda_t
:
out
std_logic
;
i2c_emio_scl_i
:
in
std_logic
;
i2c_emio_scl_o
:
out
std_logic
;
i2c_emio_scl_t
:
out
std_logic
;
i2c_emio_sda_i
:
in
std_logic
;
i2c_emio_sda_o
:
out
std_logic
;
i2c_emio_sda_t
:
out
std_logic
;
i2c_wrflash_scl_i
:
in
std_logic
;
i2c_wrflash_scl_o
:
out
std_logic
;
i2c_wrflash_scl_t
:
out
std_logic
;
i2c_wrflash_sda_i
:
in
std_logic
;
i2c_wrflash_sda_o
:
out
std_logic
;
i2c_wrflash_sda_t
:
out
std_logic
;
aur_refclk_i_clk_p
:
in
std_logic
;
aur_refclk_i_clk_n
:
in
std_logic
;
aurora_rx_0_rxp
:
in
std_logic
;
aurora_rx_0_rxn
:
in
std_logic
;
aurora_rx_1_rxp
:
in
std_logic
;
aurora_rx_1_rxn
:
in
std_logic
;
aurora_rx_2_rxp
:
in
std_logic
;
aurora_rx_2_rxn
:
in
std_logic
;
aurora_rx_3_rxp
:
in
std_logic
;
aurora_rx_3_rxn
:
in
std_logic
;
aurora_rx_4_rxp
:
in
std_logic
;
aurora_rx_4_rxn
:
in
std_logic
;
aurora_rx_5_rxp
:
in
std_logic
;
aurora_rx_5_rxn
:
in
std_logic
;
aurora_rx_6_rxp
:
in
std_logic
;
aurora_rx_6_rxn
:
in
std_logic
;
aurora_rx_7_rxp
:
in
std_logic
;
aurora_rx_7_rxn
:
in
std_logic
;
aurora_tx_0_txp
:
out
std_logic
;
aurora_tx_0_txn
:
out
std_logic
;
aurora_tx_1_txp
:
out
std_logic
;
aurora_tx_1_txn
:
out
std_logic
;
aurora_tx_2_txp
:
out
std_logic
;
aurora_tx_2_txn
:
out
std_logic
;
aurora_tx_3_txp
:
out
std_logic
;
aurora_tx_3_txn
:
out
std_logic
;
aurora_tx_4_txp
:
out
std_logic
;
aurora_tx_4_txn
:
out
std_logic
;
aurora_tx_5_txp
:
out
std_logic
;
aurora_tx_5_txn
:
out
std_logic
;
aurora_tx_6_txp
:
out
std_logic
;
aurora_tx_6_txn
:
out
std_logic
;
aurora_tx_7_txp
:
out
std_logic
;
aurora_tx_7_txn
:
out
std_logic
);
end
component
diot_v2
;
--! Signals backplane servmod
--!
@name
Signals backplane servmod
signal
s_bckpl_servmod_o
:
std_logic_vector
(
7
downto
0
);
signal
s_bckpl_servmod_i
:
std_logic_vector
(
7
downto
0
);
signal
s_bckpl_servmod_t
:
std_logic_vector
(
7
downto
0
);
--! Signals F RST buffer
--!
@name
Signals F RST buffer
signal
s_f_rst_o
:
std_logic
;
signal
s_f_rst_i
:
std_logic
;
signal
s_f_rst_t
:
std_logic
;
--! Signals I2C WR FLASH
--!
@name
Signals I2C WR FLASH
signal
s_wrflash_scl_i
:
std_logic
;
signal
s_wrflash_scl_o
:
std_logic
;
signal
s_wrflash_scl_t
:
std_logic
;
...
...
@@ -123,7 +163,7 @@ architecture structure of diot_v2_top is
signal
s_wrflash_sda_o
:
std_logic
;
signal
s_wrflash_sda_t
:
std_logic
;
--! Signals I2C Backplane
--!
@name
Signals I2C Backplane
signal
s_bckpl_scl_i
:
std_logic
;
signal
s_bckpl_scl_o
:
std_logic
;
signal
s_bckpl_scl_t
:
std_logic
;
...
...
@@ -131,7 +171,7 @@ architecture structure of diot_v2_top is
signal
s_bckpl_sda_o
:
std_logic
;
signal
s_bckpl_sda_t
:
std_logic
;
--! Signals I2C EMIO
--!
@name
Signals I2C EMIO
signal
s_emio_scl_i
:
std_logic
;
signal
s_emio_scl_o
:
std_logic
;
signal
s_emio_scl_t
:
std_logic
;
...
...
@@ -263,7 +303,41 @@ begin
i2c_wrflash_scl_t
=>
s_wrflash_scl_t
,
i2c_wrflash_sda_i
=>
s_wrflash_sda_i
,
i2c_wrflash_sda_o
=>
s_wrflash_sda_o
,
i2c_wrflash_sda_t
=>
s_wrflash_sda_t
i2c_wrflash_sda_t
=>
s_wrflash_sda_t
,
aur_refclk_i_clk_p
=>
aurora_refclk_p
,
aur_refclk_i_clk_n
=>
aurora_refclk_n
,
aurora_rx_0_rxp
=>
aurora_rx_p
(
0
),
aurora_rx_0_rxn
=>
aurora_rx_n
(
0
),
aurora_rx_1_rxp
=>
aurora_rx_p
(
1
),
aurora_rx_1_rxn
=>
aurora_rx_n
(
1
),
aurora_rx_2_rxp
=>
aurora_rx_p
(
2
),
aurora_rx_2_rxn
=>
aurora_rx_n
(
2
),
aurora_rx_3_rxp
=>
aurora_rx_p
(
3
),
aurora_rx_3_rxn
=>
aurora_rx_n
(
3
),
aurora_rx_4_rxp
=>
aurora_rx_p
(
4
),
aurora_rx_4_rxn
=>
aurora_rx_n
(
4
),
aurora_rx_5_rxp
=>
aurora_rx_p
(
5
),
aurora_rx_5_rxn
=>
aurora_rx_n
(
5
),
aurora_rx_6_rxp
=>
aurora_rx_p
(
6
),
aurora_rx_6_rxn
=>
aurora_rx_n
(
6
),
aurora_rx_7_rxp
=>
aurora_rx_p
(
7
),
aurora_rx_7_rxn
=>
aurora_rx_n
(
7
),
aurora_tx_0_txp
=>
aurora_tx_p
(
0
),
aurora_tx_0_txn
=>
aurora_tx_n
(
0
),
aurora_tx_1_txp
=>
aurora_tx_p
(
1
),
aurora_tx_1_txn
=>
aurora_tx_n
(
1
),
aurora_tx_2_txp
=>
aurora_tx_p
(
2
),
aurora_tx_2_txn
=>
aurora_tx_n
(
2
),
aurora_tx_3_txp
=>
aurora_tx_p
(
3
),
aurora_tx_3_txn
=>
aurora_tx_n
(
3
),
aurora_tx_4_txp
=>
aurora_tx_p
(
4
),
aurora_tx_4_txn
=>
aurora_tx_n
(
4
),
aurora_tx_5_txp
=>
aurora_tx_p
(
5
),
aurora_tx_5_txn
=>
aurora_tx_n
(
5
),
aurora_tx_6_txp
=>
aurora_tx_p
(
6
),
aurora_tx_6_txn
=>
aurora_tx_n
(
6
),
aurora_tx_7_txp
=>
aurora_tx_p
(
7
),
aurora_tx_7_txn
=>
aurora_tx_n
(
7
)
);
end
architecture
structure
;
...
...
gw/projects/diot_v2/tcl/create_bd.tcl
View file @
50770cf2
This source diff could not be displayed because it is too large. You can
view the blob
instead.
gw/projects/diot_v2/tcl/ps_cfg.tcl
View file @
50770cf2
...
...
@@ -622,7 +622,7 @@ MIO} \
CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ
{
600.000000
}
\
CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0
{
2
}
\
CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ
{
600
}
\
CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL
{
D
PLL
}
\
CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL
{
A
PLL
}
\
CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ
{
0
}
\
CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0
{
3
}
\
CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ
{
600
}
\
...
...
@@ -641,20 +641,20 @@ MIO} \
CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ
{
250
}
\
CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL
{
IOPLL
}
\
CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ
{
100.000000
}
\
CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0
{
5
}
\
CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0
{
12
}
\
CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ
{
100
}
\
CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL
{
IO
PLL
}
\
CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ
{
525
.000000
}
\
CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0
{
2
}
\
CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL
{
A
PLL
}
\
CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ
{
400
.000000
}
\
CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0
{
3
}
\
CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ
{
533.333
}
\
CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL
{
V
PLL
}
\
CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL
{
A
PLL
}
\
CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2
{
1
}
\
CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV
{
42
}
\
CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV
{
60
}
\
CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA
{
0.000000
}
\
CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ
{
27.138
}
\
CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL
{
PSS_REF_CLK
}
\
CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED
{
0
}
\
CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0
{
2
}
\
CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0
{
3
}
\
CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ
{
500.000000
}
\
CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0
{
3
}
\
CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ
{
500
}
\
...
...
@@ -680,9 +680,9 @@ MIO} \
CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ
{
100
}
\
CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL
{
IOPLL
}
\
CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ
{
500.000000
}
\
CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0
{
3
}
\
CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0
{
2
}
\
CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ
{
500
}
\
CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL
{
IO
PLL
}
\
CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL
{
R
PLL
}
\
CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ
{
180
}
\
CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0
{
3
}
\
CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ
{
180
}
\
...
...
@@ -740,8 +740,8 @@ MIO} \
CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL
{
PSS_REF_CLK
}
\
CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED
{
0
}
\
CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0
{
3
}
\
CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ
{
2
66.666656
}
\
CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0
{
3
}
\
CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ
{
2
50.000000
}
\
CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0
{
4
}
\
CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ
{
267
}
\
CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL
{
RPLL
}
\
CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ
{
100.000000
}
\
...
...
@@ -766,14 +766,14 @@ MIO} \
CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ
{
200
}
\
CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL
{
IOPLL
}
\
CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ
{
50.000000
}
\
CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0
{
16
}
\
CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0
{
30
}
\
CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1
{
1
}
\
CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ
{
50
}
\
CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL
{
R
PLL
}
\
CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ
{
1
00
}
\
CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0
{
4
}
\
CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL
{
IO
PLL
}
\
CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ
{
200.0000
00
}
\
CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0
{
5
}
\
CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1
{
1
}
\
CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ
{
1
00
}
\
CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ
{
2
00
}
\
CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL
{
RPLL
}
\
CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ
{
100
}
\
CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0
{
4
}
\
...
...
@@ -791,19 +791,19 @@ MIO} \
CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ
{
300
}
\
CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL
{
IOPLL
}
\
CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2
{
1
}
\
CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV
{
32
}
\
CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV
{
40
}
\
CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA
{
0.000000
}
\
CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ
{
27.138
}
\
CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL
{
PSS_REF_CLK
}
\
CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED
{
0
}
\
CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0
{
2
}
\
CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ
{
200.000000
}
\
CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0
{
4
}
\
CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0
{
5
}
\
CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1
{
1
}
\
CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ
{
200
}
\
CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL
{
RPLL
}
\
CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ
{
50.000000
}
\
CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0
{
16
}
\
CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0
{
20
}
\
CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1
{
1
}
\
CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ
{
50
}
\
CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL
{
RPLL
}
\
...
...
@@ -1023,7 +1023,7 @@ MIO} \
CONFIG.PSU__FPD_SLCR__WDT1__FREQMHZ
{
100
}
\
CONFIG.PSU__FPD_SLCR__WDT_CLK_SEL__SELECT
{
APB
}
\
CONFIG.PSU__FPGA_PL0_ENABLE
{
1
}
\
CONFIG.PSU__FPGA_PL1_ENABLE
{
0
}
\
CONFIG.PSU__FPGA_PL1_ENABLE
{
1
}
\
CONFIG.PSU__FPGA_PL2_ENABLE
{
0
}
\
CONFIG.PSU__FPGA_PL3_ENABLE
{
0
}
\
CONFIG.PSU__FP__POWER__ON
{
1
}
\
...
...
@@ -1064,7 +1064,7 @@ MIO} \
CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE
{
1
}
\
CONFIG.PSU__GPIO_EMIO_WIDTH
{
95
}
\
CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE
{
1
}
\
CONFIG.PSU__GPIO_EMIO__PERIPHERAL__IO
{
16
}
\
CONFIG.PSU__GPIO_EMIO__PERIPHERAL__IO
{
95
}
\
CONFIG.PSU__GPIO_EMIO__WIDTH
{[
94:0
]}
\
CONFIG.PSU__GPU_PP0__POWER__ON
{
0
}
\
CONFIG.PSU__GPU_PP1__POWER__ON
{
0
}
\
...
...
@@ -1199,7 +1199,7 @@ MIO} \
CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ
{
100
}
\
CONFIG.PSU__LPD_SLCR__CSUPMU__FREQMHZ
{
100
}
\
CONFIG.PSU__MAXIGP0__DATA_WIDTH
{
32
}
\
CONFIG.PSU__MAXIGP1__DATA_WIDTH
{
128
}
\
CONFIG.PSU__MAXIGP1__DATA_WIDTH
{
32
}
\
CONFIG.PSU__MAXIGP2__DATA_WIDTH
{
32
}
\
CONFIG.PSU__M_AXI_GP0_SUPPORTS_NARROW_BURST
{
1
}
\
CONFIG.PSU__M_AXI_GP1_SUPPORTS_NARROW_BURST
{
1
}
\
...
...
@@ -1295,7 +1295,7 @@ MIO} \
CONFIG.PSU__PCIE__VENDOR_ID
{}
\
CONFIG.PSU__PJTAG__PERIPHERAL__ENABLE
{
0
}
\
CONFIG.PSU__PL_CLK0_BUF
{
TRUE
}
\
CONFIG.PSU__PL_CLK1_BUF
{
FALS
E
}
\
CONFIG.PSU__PL_CLK1_BUF
{
TRU
E
}
\
CONFIG.PSU__PL_CLK2_BUF
{
FALSE
}
\
CONFIG.PSU__PL_CLK3_BUF
{
FALSE
}
\
CONFIG.PSU__PL__POWER__ON
{
1
}
\
...
...
@@ -1322,46 +1322,37 @@ MIO} \
CONFIG.PSU__PROTECTION__DEBUG
{
0
}
\
CONFIG.PSU__PROTECTION__ENABLE
{
0
}
\
CONFIG.PSU__PROTECTION__FPD_SEGMENTS
{
\
SA:0xFD1A0000
;
SIZE:1280
;
UNIT:KB
;
RegionTZ:Secure
;
WrAllowed:Read/Write
;
\
subsystemId:PMU Firmware | SA:0xFD000000
;
SIZE:64
;
UNIT:KB
;
RegionTZ:Secure
;
\
WrAllowed:Read/Write
;
subsystemId:PMU Firmware | SA:0xFD010000
;
SIZE:64
;
\
UNIT:KB
;
RegionTZ:Secure
;
WrAllowed:Read/Write
;
subsystemId:PMU Firmware |
\
SA:0xFD020000
;
SIZE:64
;
UNIT:KB
;
RegionTZ:Secure
;
WrAllowed:Read/Write
;
\
subsystemId:PMU Firmware | SA:0xFD030000
;
SIZE:64
;
UNIT:KB
;
RegionTZ:Secure
;
\
WrAllowed:Read/Write
;
subsystemId:PMU Firmware | SA:0xFD040000
;
SIZE:64
;
\
UNIT:KB
;
RegionTZ:Secure
;
WrAllowed:Read/Write
;
subsystemId:PMU Firmware |
\
SA:0xFD050000
;
SIZE:64
;
UNIT:KB
;
RegionTZ:Secure
;
WrAllowed:Read/Write
;
\
subsystemId:PMU Firmware | SA:0xFD610000
;
SIZE:512
;
UNIT:KB
;
RegionTZ:Secure
;
\
WrAllowed:Read/Write
;
subsystemId:PMU Firmware | SA:0xFD5D0000
;
SIZE:64
;
\
UNIT:KB
;
RegionTZ:Secure
;
WrAllowed:Read/Write
;
subsystemId:PMU Firmware |
\
SA:0xFD1A0000
;
SIZE:1280
;
UNIT:KB
;
RegionTZ:Secure
;
WrAllowed:Read/Write
;
\
subsystemId:Secure Subsystem
}
\
SA:0xFD1A0000
;
SIZE:1280
;
UNIT:KB
;
RegionTZ:Secure
;
WrAllowed:Read/Write
;
subsystemId:PMU Firmware |
\
SA:0xFD000000
;
SIZE:64
;
UNIT:KB
;
RegionTZ:Secure
;
WrAllowed:Read/Write
;
subsystemId:PMU Firmware |
\
SA:0xFD010000
;
SIZE:64
;
UNIT:KB
;
RegionTZ:Secure
;
WrAllowed:Read/Write
;
subsystemId:PMU Firmware |
\
SA:0xFD020000
;
SIZE:64
;
UNIT:KB
;
RegionTZ:Secure
;
WrAllowed:Read/Write
;
subsystemId:PMU Firmware |
\
SA:0xFD030000
;
SIZE:64
;
UNIT:KB
;
RegionTZ:Secure
;
WrAllowed:Read/Write
;
subsystemId:PMU Firmware |
\
SA:0xFD040000
;
SIZE:64
;
UNIT:KB
;
RegionTZ:Secure
;
WrAllowed:Read/Write
;
subsystemId:PMU Firmware |
\
SA:0xFD050000
;
SIZE:64
;
UNIT:KB
;
RegionTZ:Secure
;
WrAllowed:Read/Write
;
subsystemId:PMU Firmware |
\
SA:0xFD610000
;
SIZE:512
;
UNIT:KB
;
RegionTZ:Secure
;
WrAllowed:Read/Write
;
subsystemId:PMU Firmware |
\
SA:0xFD5D0000
;
SIZE:64
;
UNIT:KB
;
RegionTZ:Secure
;
WrAllowed:Read/Write
;
subsystemId:PMU Firmware |
\
SA:0xFD1A0000
;
SIZE:1280
;
UNIT:KB
;
RegionTZ:Secure
;
WrAllowed:Read/Write
;
subsystemId:Secure Subsystem
}
\
CONFIG.PSU__PROTECTION__LOCK_UNUSED_SEGMENTS
{
0
}
\
CONFIG.PSU__PROTECTION__LPD_SEGMENTS
{
\
SA:0xFF980000
;
SIZE:64
;
UNIT:KB
;
RegionTZ:Secure
;
WrAllowed:Read/Write
;
\
subsystemId:PMU Firmware| SA:0xFF5E0000
;
SIZE:2560
;
UNIT:KB
;
RegionTZ:Secure
;
\
WrAllowed:Read/Write
;
subsystemId:PMU Firmware| SA:0xFFCC0000
;
SIZE:64
;
\
UNIT:KB
;
RegionTZ:Secure
;
WrAllowed:Read/Write
;
subsystemId:PMU Firmware|
\
SA:0xFF180000
;
SIZE:768
;
UNIT:KB
;
RegionTZ:Secure
;
WrAllowed:Read/Write
;
\
subsystemId:PMU Firmware| SA:0xFF410000
;
SIZE:640
;
UNIT:KB
;
RegionTZ:Secure
;
\
WrAllowed:Read/Write
;
subsystemId:PMU Firmware| SA:0xFFA70000
;
SIZE:64
;
\
UNIT:KB
;
RegionTZ:Secure
;
WrAllowed:Read/Write
;
subsystemId:PMU Firmware|
\
SA:0xFF9A0000
;
SIZE:64
;
UNIT:KB
;
RegionTZ:Secure
;
WrAllowed:Read/Write
;
\
subsystemId:PMU Firmware|SA:0xFF5E0000
;
SIZE:2560
;
UNIT:KB
;
RegionTZ:Secure
;
\
WrAllowed:Read/Write
;
subsystemId:Secure Subsystem|SA:0xFFCC0000
;
SIZE:64
;
\
UNIT:KB
;
RegionTZ:Secure
;
WrAllowed:Read/Write
;
subsystemId:Secure
\
Subsystem|SA:0xFF180000
;
SIZE:768
;
UNIT:KB
;
RegionTZ:Secure
;
\
WrAllowed:Read/Write
;
subsystemId:Secure Subsystem|SA:0xFF9A0000
;
SIZE:64
;
\
UNIT:KB
;
RegionTZ:Secure
;
WrAllowed:Read/Write
;
subsystemId:Secure Subsystem
}
\
SA:0xFF980000
;
SIZE:64
;
UNIT:KB
;
RegionTZ:Secure
;
WrAllowed:Read/Write
;
subsystemId:PMU Firmware|
\
SA:0xFF5E0000
;
SIZE:2560
;
UNIT:KB
;
RegionTZ:Secure
;
WrAllowed:Read/Write
;
subsystemId:PMU Firmware|
\
SA:0xFFCC0000
;
SIZE:64
;
UNIT:KB
;
RegionTZ:Secure
;
WrAllowed:Read/Write
;
subsystemId:PMU Firmware|
\
SA:0xFF180000
;
SIZE:768
;
UNIT:KB
;
RegionTZ:Secure
;
WrAllowed:Read/Write
;
subsystemId:PMU Firmware|
\
SA:0xFF410000
;
SIZE:640
;
UNIT:KB
;
RegionTZ:Secure
;
WrAllowed:Read/Write
;
subsystemId:PMU Firmware|
\
SA:0xFFA70000
;
SIZE:64
;
UNIT:KB
;
RegionTZ:Secure
;
WrAllowed:Read/Write
;
subsystemId:PMU Firmware|
\
SA:0xFF9A0000
;
SIZE:64
;
UNIT:KB
;
RegionTZ:Secure
;
WrAllowed:Read/Write
;
subsystemId:PMU Firmware|
\
SA:0xFF5E0000
;
SIZE:2560
;
UNIT:KB
;
RegionTZ:Secure
;
WrAllowed:Read/Write
;
subsystemId:Secure Subsystem|
\
SA:0xFFCC0000
;
SIZE:64
;
UNIT:KB
;
RegionTZ:Secure
;
WrAllowed:Read/Write
;
subsystemId:Secure Subsystem|
\
SA:0xFF180000
;
SIZE:768
;
UNIT:KB
;
RegionTZ:Secure
;
WrAllowed:Read/Write
;
subsystemId:Secure Subsystem|
\
SA:0xFF9A0000
;
SIZE:64
;
UNIT:KB
;
RegionTZ:Secure
;
WrAllowed:Read/Write
;
subsystemId:Secure Subsystem
}
\
CONFIG.PSU__PROTECTION__MASTERS
{
\
USB1:NonSecure
;
0|USB0:NonSecure
;
0|S_AXI_LPD:NA
;
0|S_AXI_HPC1_FPD:NA
;
0|S_AXI_HPC0_FPD:NA
;
0
|S_AXI_HP3_FPD:NA
;
0|S_AXI_HP2_FPD:NA
;
0|S_AXI_HP1_FPD:NA
;
0|S_AXI_HP0_FPD:NA
;
0|S_AXI_ACP:NA
;
0|S_AXI_ACE:NA
;
0|SD1:NonSecure
;
1|SD0:NonSecure
;
1|SATA1:NonSecure
;
0|SATA0:NonSecure
;
0|RPU1:Secure
;
1|RPU0:Secure
;
1|QSPI:NonSecure
;
1|PMU:NA
;
1|PCIe:NonSecure
;
0|NAND:NonSecure
;
0|LDMA:NonSecure
;
1|GPU:NonSecure
;
1|GEM3:NonSecure
;
0|GEM2:NonSecure
;
0|GEM1:NonSecure
;
0|GEM0:NonSecure
;
1|FDMA:NonSecure
;
1|DP:NonSecure
;
0|DAP:NA
;
1|Coresight:NA
;
1|CSU:NA
;
1|APU:NA
;
1
}
\
USB1:NonSecure
;
0|USB0:NonSecure
;
0|S_AXI_LPD:NA
;
0|S_AXI_HPC1_FPD:NA
;
0|S_AXI_HPC0_FPD:NA
;
1
|S_AXI_HP3_FPD:NA
;
0|S_AXI_HP2_FPD:NA
;
0|S_AXI_HP1_FPD:NA
;
0|S_AXI_HP0_FPD:NA
;
0|S_AXI_ACP:NA
;
0|S_AXI_ACE:NA
;
0|SD1:NonSecure
;
1|SD0:NonSecure
;
1|SATA1:NonSecure
;
0|SATA0:NonSecure
;
0|RPU1:Secure
;
1|RPU0:Secure
;
1|QSPI:NonSecure
;
1|PMU:NA
;
1|PCIe:NonSecure
;
0|NAND:NonSecure
;
0|LDMA:NonSecure
;
1|GPU:NonSecure
;
1|GEM3:NonSecure
;
0|GEM2:NonSecure
;
0|GEM1:NonSecure
;
0|GEM0:NonSecure
;
1|FDMA:NonSecure
;
1|DP:NonSecure
;
0|DAP:NA
;
1|Coresight:NA
;
1|CSU:NA
;
1|APU:NA
;
1
}
\
CONFIG.PSU__PROTECTION__MASTERS_TZ
{
\
GEM0:NonSecure|SD1:NonSecure|GEM2:NonSecure|GEM1:NonSecure|GEM3:NonSecure|PCIe:NonSecure|DP:NonSecure|NAND:NonSecure|GPU:NonSecure|USB1:NonSecure|USB0:NonSecure|LDMA:NonSecure|FDMA:NonSecure|QSPI:NonSecure|SD0:NonSecure
}
\
CONFIG.PSU__PROTECTION__OCM_SEGMENTS
{
NONE
}
\
CONFIG.PSU__PROTECTION__PRESUBSYSTEMS
{
NONE
}
\
CONFIG.PSU__PROTECTION__SLAVES
{
\
LPD
;
USB3_1_XHCI
;
FE300000
;
FE3FFFFF
;
0|LPD
;
USB3_1
;
FF9E0000
;
FF9EFFFF
;
0|LPD
;
USB3_0_XHCI
;
FE200000
;
FE2FFFFF
;
0|LPD
;
USB3_0
;
FF9D0000
;
FF9DFFFF
;
0|LPD
;
UART1
;
FF010000
;
FF01FFFF
;
0|LPD
;
UART0
;
FF000000
;
FF00FFFF
;
1|LPD
;
TTC3
;
FF140000
;
FF14FFFF
;
0|LPD
;
TTC2
;
FF130000
;
FF13FFFF
;
0|LPD
;
TTC1
;
FF120000
;
FF12FFFF
;
0|LPD
;
TTC0
;
FF110000
;
FF11FFFF
;
1|FPD
;
SWDT1
;
FD4D0000
;
FD4DFFFF
;
0|LPD
;
SWDT0
;
FF150000
;
FF15FFFF
;
0|LPD
;
SPI1
;
FF050000
;
FF05FFFF
;
0|LPD
;
SPI0
;
FF040000
;
FF04FFFF
;
0|FPD
;
SMMU_REG
;
FD5F0000
;
FD5FFFFF
;
1|FPD
;
SMMU
;
FD800000
;
FDFFFFFF
;
1|FPD
;
SIOU
;
FD3D0000
;
FD3DFFFF
;
1|FPD
;
SERDES
;
FD400000
;
FD47FFFF
;
1|LPD
;
SD1
;
FF170000
;
FF17FFFF
;
1|LPD
;
SD0
;
FF160000
;
FF16FFFF
;
1|FPD
;
SATA
;
FD0C0000
;
FD0CFFFF
;
0|LPD
;
RTC
;
FFA60000
;
FFA6FFFF
;
1|LPD
;
RSA_CORE
;
FFCE0000
;
FFCEFFFF
;
1|LPD
;
RPU
;
FF9A0000
;
FF9AFFFF
;
1|LPD
;
R5_TCM_RAM_GLOBAL
;
FFE00000
;
FFE3FFFF
;
1|LPD
;
R5_1_Instruction_Cache
;
FFEC0000
;
FFECFFFF
;
1|LPD
;
R5_1_Data_Cache
;
FFED0000
;
FFEDFFFF
;
1|LPD
;
R5_1_BTCM_GLOBAL
;
FFEB0000
;
FFEBFFFF
;
1|LPD
;
R5_1_ATCM_GLOBAL
;
FFE90000
;
FFE9FFFF
;
1|LPD
;
R5_0_Instruction_Cache
;
FFE40000
;
FFE4FFFF
;
1|LPD
;
R5_0_Data_Cache
;
FFE50000
;
FFE5FFFF
;
1|LPD
;
R5_0_BTCM_GLOBAL
;
FFE20000
;
FFE2FFFF
;
1|LPD
;
R5_0_ATCM_GLOBAL
;
FFE00000
;
FFE0FFFF
;
1|LPD
;
QSPI_Linear_Address
;
C0000000
;
DFFFFFFF
;
1|LPD
;
QSPI
;
FF0F0000
;
FF0FFFFF
;
1|LPD
;
PMU_RAM
;
FFDC0000
;
FFDDFFFF
;
1|LPD
;
PMU_GLOBAL
;
FFD80000
;
FFDBFFFF
;
1|FPD
;
PCIE_MAIN
;
FD0E0000
;
FD0EFFFF
;
0|FPD
;
PCIE_LOW
;
E0000000
;
EFFFFFFF
;
0|FPD
;
PCIE_HIGH2
;
8000000000
;
BFFFFFFFFF
;
0|FPD
;
PCIE_HIGH1
;
600000000
;
7FFFFFFFF
;
0|FPD
;
PCIE_DMA
;
FD0F0000
;
FD0FFFFF
;
0|FPD
;
PCIE_ATTRIB
;
FD480000
;
FD48FFFF
;
0|LPD
;
OCM_XMPU_CFG
;
FFA70000
;
FFA7FFFF
;
1|LPD
;
OCM_SLCR
;
FF960000
;
FF96FFFF
;
1|OCM
;
OCM
;
FFFC0000
;
FFFFFFFF
;
1|LPD
;
NAND
;
FF100000
;
FF10FFFF
;
0|LPD
;
MBISTJTAG
;
FFCF0000
;
FFCFFFFF
;
1|LPD
;
LPD_XPPU_SINK
;
FF9C0000
;
FF9CFFFF
;
1|LPD
;
LPD_XPPU
;
FF980000
;
FF98FFFF
;
1|LPD
;
LPD_SLCR_SECURE
;
FF4B0000
;
FF4DFFFF
;
1|LPD
;
LPD_SLCR
;
FF410000
;
FF4AFFFF
;
1|LPD
;
LPD_GPV
;
FE100000
;
FE1FFFFF
;
1|LPD
;
LPD_DMA_7
;
FFAF0000
;
FFAFFFFF
;
1|LPD
;
LPD_DMA_6
;
FFAE0000
;
FFAEFFFF
;
1|LPD
;
LPD_DMA_5
;
FFAD0000
;
FFADFFFF
;
1|LPD
;
LPD_DMA_4
;
FFAC0000
;
FFACFFFF
;
1|LPD
;
LPD_DMA_3
;
FFAB0000
;
FFABFFFF
;
1|LPD
;
LPD_DMA_2
;
FFAA0000
;
FFAAFFFF
;
1|LPD
;
LPD_DMA_1
;
FFA90000
;
FFA9FFFF
;
1|LPD
;
LPD_DMA_0
;
FFA80000
;
FFA8FFFF
;
1|LPD
;
IPI_CTRL
;
FF380000
;
FF3FFFFF
;
1|LPD
;
IOU_SLCR
;
FF180000
;
FF23FFFF
;
1|LPD
;
IOU_SECURE_SLCR
;
FF240000
;
FF24FFFF
;
1|LPD
;
IOU_SCNTRS
;
FF260000
;
FF26FFFF
;
1|LPD
;
IOU_SCNTR
;
FF250000
;
FF25FFFF
;
1|LPD
;
IOU_GPV
;
FE000000
;
FE0FFFFF
;
1|LPD
;
I2C1
;
FF030000
;
FF03FFFF
;
1|LPD
;
I2C0
;
FF020000
;
FF02FFFF
;
1|FPD
;
GPU
;
FD4B0000
;
FD4BFFFF
;
0|LPD
;
GPIO
;
FF0A0000
;
FF0AFFFF
;
1|LPD
;
GEM3
;
FF0E0000
;
FF0EFFFF
;
0|LPD
;
GEM2
;
FF0D0000
;
FF0DFFFF
;
0|LPD
;
GEM1
;
FF0C0000
;
FF0CFFFF
;
0|LPD
;
GEM0
;
FF0B0000
;
FF0BFFFF
;
1|FPD
;
FPD_XMPU_SINK
;
FD4F0000
;
FD4FFFFF
;
1|FPD
;
FPD_XMPU_CFG
;
FD5D0000
;
FD5DFFFF
;
1|FPD
;
FPD_SLCR_SECURE
;
FD690000
;
FD6CFFFF
;
1|FPD
;
FPD_SLCR
;
FD610000
;
FD68FFFF
;
1|FPD
;
FPD_DMA_CH7
;
FD570000
;
FD57FFFF
;
1|FPD
;
FPD_DMA_CH6
;
FD560000
;
FD56FFFF
;
1|FPD
;
FPD_DMA_CH5
;
FD550000
;
FD55FFFF
;
1|FPD
;
FPD_DMA_CH4
;
FD540000
;
FD54FFFF
;
1|FPD
;
FPD_DMA_CH3
;
FD530000
;
FD53FFFF
;
1|FPD
;
FPD_DMA_CH2
;
FD520000
;
FD52FFFF
;
1|FPD
;
FPD_DMA_CH1
;
FD510000
;
FD51FFFF
;
1|FPD
;
FPD_DMA_CH0
;
FD500000
;
FD50FFFF
;
1|LPD
;
EFUSE
;
FFCC0000
;
FFCCFFFF
;
1|FPD
;
Display
\
Port
;
FD4A0000
;
FD4AFFFF
;
0|FPD
;
DPDMA
;
FD4C0000
;
FD4CFFFF
;
0|FPD
;
DDR_XMPU5_CFG
;
FD050000
;
FD05FFFF
;
1|FPD
;
DDR_XMPU4_CFG
;
FD040000
;
FD04FFFF
;
1|FPD
;
DDR_XMPU3_CFG
;
FD030000
;
FD03FFFF
;
1|FPD
;
DDR_XMPU2_CFG
;
FD020000
;
FD02FFFF
;
1|FPD
;
DDR_XMPU1_CFG
;
FD010000
;
FD01FFFF
;
1|FPD
;
DDR_XMPU0_CFG
;
FD000000
;
FD00FFFF
;
1|FPD
;
DDR_QOS_CTRL
;
FD090000
;
FD09FFFF
;
1|FPD
;
DDR_PHY
;
FD080000
;
FD08FFFF
;
1|DDR
;
DDR_LOW
;
0
;
7FFFFFFF
;
1|DDR
;
DDR_HIGH
;
800000000
;
87FFFFFFF
;
1|FPD
;
DDDR_CTRL
;
FD070000
;
FD070FFF
;
1|LPD
;
Coresight
;
FE800000
;
FEFFFFFF
;
1|LPD
;
CSU_DMA
;
FFC80000
;
FFC9FFFF
;
1|LPD
;
CSU
;
FFCA0000
;
FFCAFFFF
;
1|LPD
;
CRL_APB
;
FF5E0000
;
FF85FFFF
;
1|FPD
;
CRF_APB
;
FD1A0000
;
FD2DFFFF
;
1|FPD
;
CCI_REG
;
FD5E0000
;
FD5EFFFF
;
1|LPD
;
CAN1
;
FF070000
;
FF07FFFF
;
0|LPD
;
CAN0
;
FF060000
;
FF06FFFF
;
0|FPD
;
APU
;
FD5C0000
;
FD5CFFFF
;
1|LPD
;
APM_INTC_IOU
;
FFA20000
;
FFA2FFFF
;
1|LPD
;
APM_FPD_LPD
;
FFA30000
;
FFA3FFFF
;
1|FPD
;
APM_5
;
FD490000
;
FD49FFFF
;
1|FPD
;
APM_0
;
FD0B0000
;
FD0BFFFF
;
1|LPD
;
APM2
;
FFA10000
;
FFA1FFFF
;
1|LPD
;
APM1
;
FFA00000
;
FFA0FFFF
;
1|LPD
;
AMS
;
FFA50000
;
FFA5FFFF
;
1|FPD
;
AFI_5
;
FD3B0000
;
FD3BFFFF
;
1|FPD
;
AFI_4
;
FD3A0000
;
FD3AFFFF
;
1|FPD
;
AFI_3
;
FD390000
;
FD39FFFF
;
1|FPD
;
AFI_2
;
FD380000
;
FD38FFFF
;
1|FPD
;
AFI_1
;
FD370000
;
FD37FFFF
;
1|FPD
;
AFI_0
;
FD360000
;
FD36FFFF
;
1|LPD
;
AFIFM6
;
FF9B0000
;
FF9BFFFF
;
1|FPD
;
ACPU_GIC
;
F9010000
;
F907FFFF
;
1
}
\
LPD
;
USB3_1_XHCI
;
FE300000
;
FE3FFFFF
;
0|LPD
;
USB3_1
;
FF9E0000
;
FF9EFFFF
;
0|LPD
;
USB3_0_XHCI
;
FE200000
;
FE2FFFFF
;
0|LPD
;
USB3_0
;
FF9D0000
;
FF9DFFFF
;
0|LPD
;
UART1
;
FF010000
;
FF01FFFF
;
0|LPD
;
UART0
;
FF000000
;
FF00FFFF
;
1|LPD
;
TTC3
;
FF140000
;
FF14FFFF
;
0|LPD
;
TTC2
;
FF130000
;
FF13FFFF
;
0|LPD
;
TTC1
;
FF120000
;
FF12FFFF
;
0|LPD
;
TTC0
;
FF110000
;
FF11FFFF
;
1|FPD
;
SWDT1
;
FD4D0000
;
FD4DFFFF
;
0|LPD
;
SWDT0
;
FF150000
;
FF15FFFF
;
0|LPD
;
SPI1
;
FF050000
;
FF05FFFF
;
0|LPD
;
SPI0
;
FF040000
;
FF04FFFF
;
0|FPD
;
SMMU_REG
;
FD5F0000
;
FD5FFFFF
;
1|FPD
;
SMMU
;
FD800000
;
FDFFFFFF
;
1|FPD
;
SIOU
;
FD3D0000
;
FD3DFFFF
;
1|FPD
;
SERDES
;
FD400000
;
FD47FFFF
;
1|LPD
;
SD1
;
FF170000
;
FF17FFFF
;
1|LPD
;
SD0
;
FF160000
;
FF16FFFF
;
1|FPD
;
SATA
;
FD0C0000
;
FD0CFFFF
;
0|LPD
;
RTC
;
FFA60000
;
FFA6FFFF
;
1|LPD
;
RSA_CORE
;
FFCE0000
;
FFCEFFFF
;
1|LPD
;
RPU
;
FF9A0000
;
FF9AFFFF
;
1|LPD
;
R5_TCM_RAM_GLOBAL
;
FFE00000
;
FFE3FFFF
;
1|LPD
;
R5_1_Instruction_Cache
;
FFEC0000
;
FFECFFFF
;
1|LPD
;
R5_1_Data_Cache
;
FFED0000
;
FFEDFFFF
;
1|LPD
;
R5_1_BTCM_GLOBAL
;
FFEB0000
;
FFEBFFFF
;
1|LPD
;
R5_1_ATCM_GLOBAL
;
FFE90000
;
FFE9FFFF
;
1|LPD
;
R5_0_Instruction_Cache
;
FFE40000
;
FFE4FFFF
;
1|LPD
;
R5_0_Data_Cache
;
FFE50000
;
FFE5FFFF
;
1|LPD
;
R5_0_BTCM_GLOBAL
;
FFE20000
;
FFE2FFFF
;
1|LPD
;
R5_0_ATCM_GLOBAL
;
FFE00000
;
FFE0FFFF
;
1|LPD
;
QSPI_Linear_Address
;
C0000000
;
DFFFFFFF
;
1|LPD
;
QSPI
;
FF0F0000
;
FF0FFFFF
;
1|LPD
;
PMU_RAM
;
FFDC0000
;
FFDDFFFF
;
1|LPD
;
PMU_GLOBAL
;
FFD80000
;
FFDBFFFF
;
1|FPD
;
PCIE_MAIN
;
FD0E0000
;
FD0EFFFF
;
0|FPD
;
PCIE_LOW
;
E0000000
;
EFFFFFFF
;
0|FPD
;
PCIE_HIGH2
;
8000000000
;
BFFFFFFFFF
;
0|FPD
;
PCIE_HIGH1
;
600000000
;
7FFFFFFFF
;
0|FPD
;
PCIE_DMA
;
FD0F0000
;
FD0FFFFF
;
0|FPD
;
PCIE_ATTRIB
;
FD480000
;
FD48FFFF
;
0|LPD
;
OCM_XMPU_CFG
;
FFA70000
;
FFA7FFFF
;
1|LPD
;
OCM_SLCR
;
FF960000
;
FF96FFFF
;
1|OCM
;
OCM
;
FFFC0000
;
FFFFFFFF
;
1|LPD
;
NAND
;
FF100000
;
FF10FFFF
;
0|LPD
;
MBISTJTAG
;
FFCF0000
;
FFCFFFFF
;
1|LPD
;
LPD_XPPU_SINK
;
FF9C0000
;
FF9CFFFF
;
1|LPD
;
LPD_XPPU
;
FF980000
;
FF98FFFF
;
1|LPD
;
LPD_SLCR_SECURE
;
FF4B0000
;
FF4DFFFF
;
1|LPD
;
LPD_SLCR
;
FF410000
;
FF4AFFFF
;
1|LPD
;
LPD_GPV
;
FE100000
;
FE1FFFFF
;
1|LPD
;
LPD_DMA_7
;
FFAF0000
;
FFAFFFFF
;
1|LPD
;
LPD_DMA_6
;
FFAE0000
;
FFAEFFFF
;
1|LPD
;
LPD_DMA_5
;
FFAD0000
;
FFADFFFF
;
1|LPD
;
LPD_DMA_4
;
FFAC0000
;
FFACFFFF
;
1|LPD
;
LPD_DMA_3
;
FFAB0000
;
FFABFFFF
;
1|LPD
;
LPD_DMA_2
;
FFAA0000
;
FFAAFFFF
;
1|LPD
;
LPD_DMA_1
;
FFA90000
;
FFA9FFFF
;
1|LPD
;
LPD_DMA_0
;
FFA80000
;
FFA8FFFF
;
1|LPD
;
IPI_CTRL
;
FF380000
;
FF3FFFFF
;
1|LPD
;
IOU_SLCR
;
FF180000
;
FF23FFFF
;
1|LPD
;
IOU_SECURE_SLCR
;
FF240000
;
FF24FFFF
;
1|LPD
;
IOU_SCNTRS
;
FF260000
;
FF26FFFF
;
1|LPD
;
IOU_SCNTR
;
FF250000
;
FF25FFFF
;
1|LPD
;
IOU_GPV
;
FE000000
;
FE0FFFFF
;
1|LPD
;
I2C1
;
FF030000
;
FF03FFFF
;
1|LPD
;
I2C0
;
FF020000
;
FF02FFFF
;
1|FPD
;
GPU
;
FD4B0000
;
FD4BFFFF
;
0|LPD
;
GPIO
;
FF0A0000
;
FF0AFFFF
;
1|LPD
;
GEM3
;
FF0E0000
;
FF0EFFFF
;
0|LPD
;
GEM2
;
FF0D0000
;
FF0DFFFF
;
0|LPD
;
GEM1
;
FF0C0000
;
FF0CFFFF
;
0|LPD
;
GEM0
;
FF0B0000
;
FF0BFFFF
;
1|FPD
;
FPD_XMPU_SINK
;
FD4F0000
;
FD4FFFFF
;
1|FPD
;
FPD_XMPU_CFG
;
FD5D0000
;
FD5DFFFF
;
1|FPD
;
FPD_SLCR_SECURE
;
FD690000
;
FD6CFFFF
;
1|FPD
;
FPD_SLCR
;
FD610000
;
FD68FFFF
;
1|FPD
;
FPD_GPV
;
FD700000
;
FD7FFFFF
;
1|FPD
;
FPD_DMA_CH7
;
FD570000
;
FD57FFFF
;
1|FPD
;
FPD_DMA_CH6
;
FD560000
;
FD56FFFF
;
1|FPD
;
FPD_DMA_CH5
;
FD550000
;
FD55FFFF
;
1|FPD
;
FPD_DMA_CH4
;
FD540000
;
FD54FFFF
;
1|FPD
;
FPD_DMA_CH3
;
FD530000
;
FD53FFFF
;
1|FPD
;
FPD_DMA_CH2
;
FD520000
;
FD52FFFF
;
1|FPD
;
FPD_DMA_CH1
;
FD510000
;
FD51FFFF
;
1|FPD
;
FPD_DMA_CH0
;
FD500000
;
FD50FFFF
;
1|LPD
;
EFUSE
;
FFCC0000
;
FFCCFFFF
;
1|FPD
;
Display Port
;
FD4A0000
;
FD4AFFFF
;
0|FPD
;
DPDMA
;
FD4C0000
;
FD4CFFFF
;
0|FPD
;
DDR_XMPU5_CFG
;
FD050000
;
FD05FFFF
;
1|FPD
;
DDR_XMPU4_CFG
;
FD040000
;
FD04FFFF
;
1|FPD
;
DDR_XMPU3_CFG
;
FD030000
;
FD03FFFF
;
1|FPD
;
DDR_XMPU2_CFG
;
FD020000
;
FD02FFFF
;
1|FPD
;
DDR_XMPU1_CFG
;
FD010000
;
FD01FFFF
;
1|FPD
;
DDR_XMPU0_CFG
;
FD000000
;
FD00FFFF
;
1|FPD
;
DDR_QOS_CTRL
;
FD090000
;
FD09FFFF
;
1|FPD
;
DDR_PHY
;
FD080000
;
FD08FFFF
;
1|DDR
;
DDR_LOW
;
0
;
7FFFFFFF
;
1|DDR
;
DDR_HIGH
;
800000000
;
87FFFFFFF
;
1|FPD
;
DDDR_CTRL
;
FD070000
;
FD070FFF
;
1|LPD
;
Coresight
;
FE800000
;
FEFFFFFF
;
1|LPD
;
CSU_DMA
;
FFC80000
;
FFC9FFFF
;
1|LPD
;
CSU
;
FFCA0000
;
FFCAFFFF
;
0|LPD
;
CRL_APB
;
FF5E0000
;
FF85FFFF
;
1|FPD
;
CRF_APB
;
FD1A0000
;
FD2DFFFF
;
1|FPD
;
CCI_REG
;
FD5E0000
;
FD5EFFFF
;
1|FPD
;
CCI_GPV
;
FD6E0000
;
FD6EFFFF
;
1|LPD
;
CAN1
;
FF070000
;
FF07FFFF
;
0|LPD
;
CAN0
;
FF060000
;
FF06FFFF
;
0|FPD
;
APU
;
FD5C0000
;
FD5CFFFF
;
1|LPD
;
APM_INTC_IOU
;
FFA20000
;
FFA2FFFF
;
1|LPD
;
APM_FPD_LPD
;
FFA30000
;
FFA3FFFF
;
1|FPD
;
APM_5
;
FD490000
;
FD49FFFF
;
1|FPD
;
APM_0
;
FD0B0000
;
FD0BFFFF
;
1|LPD
;
APM2
;
FFA10000
;
FFA1FFFF
;
1|LPD
;
APM1
;
FFA00000
;
FFA0FFFF
;
1|LPD
;
AMS
;
FFA50000
;
FFA5FFFF
;
1|FPD
;
AFI_5
;
FD3B0000
;
FD3BFFFF
;
1|FPD
;
AFI_4
;
FD3A0000
;
FD3AFFFF
;
1|FPD
;
AFI_3
;
FD390000
;
FD39FFFF
;
1|FPD
;
AFI_2
;
FD380000
;
FD38FFFF
;
1|FPD
;
AFI_1
;
FD370000
;
FD37FFFF
;
1|FPD
;
AFI_0
;
FD360000
;
FD36FFFF
;
1|LPD
;
AFIFM6
;
FF9B0000
;
FF9BFFFF
;
1|FPD
;
ACPU_GIC
;
F9010000
;
F907FFFF
;
1
}
\
CONFIG.PSU__PROTECTION__SUBSYSTEMS
{
PMU Firmware:PMU|Secure Subsystem:
}
\
CONFIG.PSU__PSS_ALT_REF_CLK__ENABLE
{
0
}
\
CONFIG.PSU__PSS_ALT_REF_CLK__FREQMHZ
{
33.333
}
\
...
...
@@ -1379,7 +1370,7 @@ Port;FD4A0000;FD4AFFFF;0|FPD;DPDMA;FD4C0000;FD4CFFFF;0|FPD;DDR_XMPU5_CFG;FD05000
CONFIG.PSU__SATA__LANE0__ENABLE
{
0
}
\
CONFIG.PSU__SATA__LANE1__ENABLE
{
0
}
\
CONFIG.PSU__SATA__PERIPHERAL__ENABLE
{
0
}
\
CONFIG.PSU__SAXIGP0__DATA_WIDTH
{
128
}
\
CONFIG.PSU__SAXIGP0__DATA_WIDTH
{
32
}
\
CONFIG.PSU__SAXIGP1__DATA_WIDTH
{
128
}
\
CONFIG.PSU__SAXIGP2__DATA_WIDTH
{
128
}
\
CONFIG.PSU__SAXIGP3__DATA_WIDTH
{
128
}
\
...
...
@@ -1494,7 +1485,7 @@ Port;FD4A0000;FD4AFFFF;0|FPD;DPDMA;FD4C0000;FD4CFFFF;0|FPD;DDR_XMPU5_CFG;FD05000
CONFIG.PSU__USE__IRQ0
{
1
}
\
CONFIG.PSU__USE__IRQ1
{
0
}
\
CONFIG.PSU__USE__M_AXI_GP0
{
0
}
\
CONFIG.PSU__USE__M_AXI_GP1
{
0
}
\
CONFIG.PSU__USE__M_AXI_GP1
{
1
}
\
CONFIG.PSU__USE__M_AXI_GP2
{
1
}
\
CONFIG.PSU__USE__PROC_EVENT_BUS
{
0
}
\
CONFIG.PSU__USE__RPU_LEGACY_INTERRUPT
{
0
}
\
...
...
@@ -1506,7 +1497,7 @@ Port;FD4A0000;FD4AFFFF;0|FPD;DPDMA;FD4C0000;FD4CFFFF;0|FPD;DDR_XMPU5_CFG;FD05000
CONFIG.PSU__USE__STM
{
0
}
\
CONFIG.PSU__USE__S_AXI_ACE
{
0
}
\
CONFIG.PSU__USE__S_AXI_ACP
{
0
}
\
CONFIG.PSU__USE__S_AXI_GP0
{
0
}
\
CONFIG.PSU__USE__S_AXI_GP0
{
1
}
\
CONFIG.PSU__USE__S_AXI_GP1
{
0
}
\
CONFIG.PSU__USE__S_AXI_GP2
{
0
}
\
CONFIG.PSU__USE__S_AXI_GP3
{
0
}
\
...
...
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