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DIOT Zynq Ultrascale-based System Board
DIOT Zynq Ultrascale-based System Board
Commit 50770cf2 authored by Adrian Byszuk's avatar Adrian Byszuk
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GW: add Chip2Chip/Aurora subsystem to BD

parent a23c7dbd
Pipeline #3842 passed with stages
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      gw/projects/diot_v2/constraints/diot_v2.xdc
      View file @ 50770cf2
      ......@@ -5,9 +5,11 @@
      # ##############################################################################
      # ------------------------------------------------------------------------------
      # GT REG CLK: 125 MHz
      # GT REF CLK: 125 MHz
      set_property PACKAGE_PIN AH10 [get_ports {gtrefclk_in_clk_p}]
      create_clock -period 8.000 -name gt_ref_clk -waveform {0.000 4.000} [get_ports {gtrefclk_in_clk_p}]
      set_property PACKAGE_PIN AA12 [get_ports {aurora_refclk_p}]
      create_clock -period 8.000 -name aurora_ref_clk [get_ports {aurora_refclk_p}]
      # ------------------------------------------------------------------------------
      # Clock Selector
      ......@@ -62,7 +64,7 @@ set_property PACKAGE_PIN AJ8 [get_ports sfp_txp]
      set_property PACKAGE_PIN AJ7 [get_ports sfp_txn]
      # ------------------------------------------------------------------------------
      # Backplain
      # Backplane
      set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {bckpl_servmod_b[0]}]
      set_property -dict {PACKAGE_PIN A13 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {bckpl_servmod_b[1]}]
      set_property -dict {PACKAGE_PIN B13 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {bckpl_servmod_b[2]}]
      ......@@ -72,3 +74,14 @@ set_property -dict {PACKAGE_PIN C13 IOSTANDARD LVCMOS33 PULLUP true} [get_ports
      set_property -dict {PACKAGE_PIN D14 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {bckpl_servmod_b[6]}]
      set_property -dict {PACKAGE_PIN A15 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {bckpl_servmod_b[7]}]
      set_property -dict {PACKAGE_PIN H11 IOSTANDARD LVCMOS33} [get_ports {bckpl_rst_n_o}]
      # ------------------------------------------------------------------------------
      # Aurora GTX pins are defined in the block desing IP GUI
      # Overwriting them here will only generate placement conflicts
      # ------------------------------------------------------------------------------
      # Timing ignore for quasi-static status signals
      set_false_path -from [get_pins diot_v2_i/chip2chip_subsystem/link_*/aurora/*/*/*/CHANNEL_UP_reg/C] \
      -to [get_pins {diot_v2_i/chip2chip_subsystem/c2c_link_ctrl/*/*/rd_data_reg[0]/D}]
      set_false_path -from [get_pins diot_v2_i/chip2chip_subsystem/link_*/aurora/*/*/*/CHANNEL_HARD_ERR_reg/C] \
      -to [get_pins {diot_v2_i/chip2chip_subsystem/c2c_link_ctrl/*/*/rd_data_reg[1]/D}]
      gw/projects/diot_v2/src/diot_v2_top.vhd
      View file @ 50770cf2
      ......@@ -51,7 +51,13 @@ entity diot_v2_top is
      emio_scl_b : inout std_logic;
      emio_sda_b : inout std_logic;
      wrflash_scl_b : inout std_logic;
      wrflash_sda_b : inout std_logic
      wrflash_sda_b : inout std_logic;
      aurora_refclk_p : in std_logic;
      aurora_refclk_n : in std_logic;
      aurora_rx_p : in std_logic_vector(7 downto 0);
      aurora_rx_n : in std_logic_vector(7 downto 0);
      aurora_tx_p : out std_logic_vector(7 downto 0);
      aurora_tx_n : out std_logic_vector(7 downto 0)
      );
      end diot_v2_top;
      ......@@ -62,60 +68,94 @@ architecture structure of diot_v2_top is
      component diot_v2 is
      port (
      f_rst_i : in std_logic;
      f_rst_o : out std_logic;
      f_rst_t : out std_logic;
      psu_alert_i : in std_logic;
      p_pres_i_0 : in std_logic_vector(1 downto 0);
      pwr_cycle_req_o_0 : out std_logic;
      clk_src_sel_o : out std_logic_vector(1 downto 0);
      gtrefclk_in_clk_p : in std_logic;
      gtrefclk_in_clk_n : in std_logic;
      pl_reset_led : out std_logic;
      link_status_led : out std_logic;
      link_sync_led : out std_logic;
      mdc_clk_led : out std_logic;
      tx_disable_o : out std_logic;
      sfp_rxp : in std_logic;
      sfp_rxn : in std_logic;
      sfp_txp : out std_logic;
      sfp_txn : out std_logic;
      bckpl_rst_n_o : out std_logic;
      bckpl_servmod_i : in std_logic_vector(7 downto 0);
      bckpl_servmod_o : out std_logic_vector(7 downto 0);
      bckpl_servmod_t : out std_logic_vector(7 downto 0);
      i2c_bckpl_scl_i : in std_logic;
      i2c_bckpl_scl_o : out std_logic;
      i2c_bckpl_scl_t : out std_logic;
      i2c_bckpl_sda_i : in std_logic;
      i2c_bckpl_sda_o : out std_logic;
      i2c_bckpl_sda_t : out std_logic;
      i2c_emio_scl_i : in std_logic;
      i2c_emio_scl_o : out std_logic;
      i2c_emio_scl_t : out std_logic;
      i2c_emio_sda_i : in std_logic;
      i2c_emio_sda_o : out std_logic;
      i2c_emio_sda_t : out std_logic;
      i2c_wrflash_scl_i : in std_logic;
      i2c_wrflash_scl_o : out std_logic;
      i2c_wrflash_scl_t : out std_logic;
      i2c_wrflash_sda_i : in std_logic;
      i2c_wrflash_sda_o : out std_logic;
      i2c_wrflash_sda_t : out std_logic
      f_rst_i : in std_logic;
      f_rst_o : out std_logic;
      f_rst_t : out std_logic;
      psu_alert_i : in std_logic;
      p_pres_i_0 : in std_logic_vector(1 downto 0);
      pwr_cycle_req_o_0 : out std_logic;
      clk_src_sel_o : out std_logic_vector(1 downto 0);
      gtrefclk_in_clk_p : in std_logic;
      gtrefclk_in_clk_n : in std_logic;
      pl_reset_led : out std_logic;
      link_status_led : out std_logic;
      link_sync_led : out std_logic;
      mdc_clk_led : out std_logic;
      tx_disable_o : out std_logic;
      sfp_rxp : in std_logic;
      sfp_rxn : in std_logic;
      sfp_txp : out std_logic;
      sfp_txn : out std_logic;
      bckpl_rst_n_o : out std_logic;
      bckpl_servmod_i : in std_logic_vector(7 downto 0);
      bckpl_servmod_o : out std_logic_vector(7 downto 0);
      bckpl_servmod_t : out std_logic_vector(7 downto 0);
      i2c_bckpl_scl_i : in std_logic;
      i2c_bckpl_scl_o : out std_logic;
      i2c_bckpl_scl_t : out std_logic;
      i2c_bckpl_sda_i : in std_logic;
      i2c_bckpl_sda_o : out std_logic;
      i2c_bckpl_sda_t : out std_logic;
      i2c_emio_scl_i : in std_logic;
      i2c_emio_scl_o : out std_logic;
      i2c_emio_scl_t : out std_logic;
      i2c_emio_sda_i : in std_logic;
      i2c_emio_sda_o : out std_logic;
      i2c_emio_sda_t : out std_logic;
      i2c_wrflash_scl_i : in std_logic;
      i2c_wrflash_scl_o : out std_logic;
      i2c_wrflash_scl_t : out std_logic;
      i2c_wrflash_sda_i : in std_logic;
      i2c_wrflash_sda_o : out std_logic;
      i2c_wrflash_sda_t : out std_logic;
      aur_refclk_i_clk_p : in std_logic;
      aur_refclk_i_clk_n : in std_logic;
      aurora_rx_0_rxp : in std_logic;
      aurora_rx_0_rxn : in std_logic;
      aurora_rx_1_rxp : in std_logic;
      aurora_rx_1_rxn : in std_logic;
      aurora_rx_2_rxp : in std_logic;
      aurora_rx_2_rxn : in std_logic;
      aurora_rx_3_rxp : in std_logic;
      aurora_rx_3_rxn : in std_logic;
      aurora_rx_4_rxp : in std_logic;
      aurora_rx_4_rxn : in std_logic;
      aurora_rx_5_rxp : in std_logic;
      aurora_rx_5_rxn : in std_logic;
      aurora_rx_6_rxp : in std_logic;
      aurora_rx_6_rxn : in std_logic;
      aurora_rx_7_rxp : in std_logic;
      aurora_rx_7_rxn : in std_logic;
      aurora_tx_0_txp : out std_logic;
      aurora_tx_0_txn : out std_logic;
      aurora_tx_1_txp : out std_logic;
      aurora_tx_1_txn : out std_logic;
      aurora_tx_2_txp : out std_logic;
      aurora_tx_2_txn : out std_logic;
      aurora_tx_3_txp : out std_logic;
      aurora_tx_3_txn : out std_logic;
      aurora_tx_4_txp : out std_logic;
      aurora_tx_4_txn : out std_logic;
      aurora_tx_5_txp : out std_logic;
      aurora_tx_5_txn : out std_logic;
      aurora_tx_6_txp : out std_logic;
      aurora_tx_6_txn : out std_logic;
      aurora_tx_7_txp : out std_logic;
      aurora_tx_7_txn : out std_logic
      );
      end component diot_v2;
      --! Signals backplane servmod
      --! @name Signals backplane servmod
      signal s_bckpl_servmod_o : std_logic_vector(7 downto 0);
      signal s_bckpl_servmod_i : std_logic_vector(7 downto 0);
      signal s_bckpl_servmod_t : std_logic_vector(7 downto 0);
      --! Signals F RST buffer
      --! @name Signals F RST buffer
      signal s_f_rst_o : std_logic;
      signal s_f_rst_i : std_logic;
      signal s_f_rst_t : std_logic;
      --! Signals I2C WR FLASH
      --! @name Signals I2C WR FLASH
      signal s_wrflash_scl_i : std_logic;
      signal s_wrflash_scl_o : std_logic;
      signal s_wrflash_scl_t : std_logic;
      ......@@ -123,7 +163,7 @@ architecture structure of diot_v2_top is
      signal s_wrflash_sda_o : std_logic;
      signal s_wrflash_sda_t : std_logic;
      --! Signals I2C Backplane
      --! @name Signals I2C Backplane
      signal s_bckpl_scl_i : std_logic;
      signal s_bckpl_scl_o : std_logic;
      signal s_bckpl_scl_t : std_logic;
      ......@@ -131,7 +171,7 @@ architecture structure of diot_v2_top is
      signal s_bckpl_sda_o : std_logic;
      signal s_bckpl_sda_t : std_logic;
      --! Signals I2C EMIO
      --! @name Signals I2C EMIO
      signal s_emio_scl_i : std_logic;
      signal s_emio_scl_o : std_logic;
      signal s_emio_scl_t : std_logic;
      ......@@ -263,7 +303,41 @@ begin
      i2c_wrflash_scl_t => s_wrflash_scl_t,
      i2c_wrflash_sda_i => s_wrflash_sda_i,
      i2c_wrflash_sda_o => s_wrflash_sda_o,
      i2c_wrflash_sda_t => s_wrflash_sda_t
      i2c_wrflash_sda_t => s_wrflash_sda_t,
      aur_refclk_i_clk_p => aurora_refclk_p,
      aur_refclk_i_clk_n => aurora_refclk_n,
      aurora_rx_0_rxp => aurora_rx_p(0),
      aurora_rx_0_rxn => aurora_rx_n(0),
      aurora_rx_1_rxp => aurora_rx_p(1),
      aurora_rx_1_rxn => aurora_rx_n(1),
      aurora_rx_2_rxp => aurora_rx_p(2),
      aurora_rx_2_rxn => aurora_rx_n(2),
      aurora_rx_3_rxp => aurora_rx_p(3),
      aurora_rx_3_rxn => aurora_rx_n(3),
      aurora_rx_4_rxp => aurora_rx_p(4),
      aurora_rx_4_rxn => aurora_rx_n(4),
      aurora_rx_5_rxp => aurora_rx_p(5),
      aurora_rx_5_rxn => aurora_rx_n(5),
      aurora_rx_6_rxp => aurora_rx_p(6),
      aurora_rx_6_rxn => aurora_rx_n(6),
      aurora_rx_7_rxp => aurora_rx_p(7),
      aurora_rx_7_rxn => aurora_rx_n(7),
      aurora_tx_0_txp => aurora_tx_p(0),
      aurora_tx_0_txn => aurora_tx_n(0),
      aurora_tx_1_txp => aurora_tx_p(1),
      aurora_tx_1_txn => aurora_tx_n(1),
      aurora_tx_2_txp => aurora_tx_p(2),
      aurora_tx_2_txn => aurora_tx_n(2),
      aurora_tx_3_txp => aurora_tx_p(3),
      aurora_tx_3_txn => aurora_tx_n(3),
      aurora_tx_4_txp => aurora_tx_p(4),
      aurora_tx_4_txn => aurora_tx_n(4),
      aurora_tx_5_txp => aurora_tx_p(5),
      aurora_tx_5_txn => aurora_tx_n(5),
      aurora_tx_6_txp => aurora_tx_p(6),
      aurora_tx_6_txn => aurora_tx_n(6),
      aurora_tx_7_txp => aurora_tx_p(7),
      aurora_tx_7_txn => aurora_tx_n(7)
      );
      end architecture structure;
      ......
      gw/projects/diot_v2/tcl/create_bd.tcl
      View file @ 50770cf2
      This source diff could not be displayed because it is too large. You can view the blob instead.
      gw/projects/diot_v2/tcl/ps_cfg.tcl
      View file @ 50770cf2
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