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DIOT Zynq Ultrascale-based System Board
DIOT Zynq Ultrascale-based System Board
Commit 402014aa authored by Alén Arias Vázquez's avatar Alén Arias Vázquez 😎
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added fpga device

parent 27fc4b68
Pipeline #3647 failed with stages
      in 47 minutes and 16 seconds
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      gw/build_project.tcl
      View file @ 402014aa
      ......@@ -26,6 +26,12 @@ source ${target_path}/tcl/create_bd.tcl -notrace
      # Create project
      create_project ${_xil_proj_name_} ${output_path}/${_xil_proj_name_} -part ${reference_part}
      # Source TCL FPGA Device
      source common-ip/fpga_device/tcl/fpga_device.tcl
      create_fpga_version "${_xil_proj_name_}" "common-ip/fpga_device/src/fpga_device.v" "${output_path}/${_xil_proj_name_}/fpga_device.v"
      add_files -norecurse common-ip/fpga_device/src/dna_reader.v
      add_files -norecurse ${output_path}/${_xil_proj_name_}/fpga_device.v
      # Set Properties from the list
      if [ info exist ::user_list(PROP_NAME) ] {
      set curr_project [ current_project ]
      ......
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