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DIOT Zynq Ultrascale-based System Board
DIOT Zynq Ultrascale-based System Board
Commit 03549333 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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adding layout v1.0 after CERN reviews and fixes

parent 506c0b2e
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hw/DIOT_System_Board.OutJob 0 → 100644
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hw/DIOT_System_Board.PrjPcb
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......@@ -718,6 +718,23 @@ GenerateClassCluster=0
DocumentUniqueId=
[Document41]
DocumentPath=pcb\DIOT_System_Board.PcbDoc
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None
DItemRevisionGUID=
GenerateClassCluster=0
DocumentUniqueId=HYSSMMET
[Document42]
DocumentPath=sch\i2c_mux.Harness
AnnotationEnabled=1
AnnotateStartValue=1
......@@ -734,7 +751,7 @@ DItemRevisionGUID=
GenerateClassCluster=0
DocumentUniqueId=
[Document42]
[Document43]
DocumentPath=sch\fpga-pl-mgts.Harness
AnnotationEnabled=1
AnnotateStartValue=1
......@@ -751,7 +768,7 @@ DItemRevisionGUID=
GenerateClassCluster=0
DocumentUniqueId=
[Document43]
[Document44]
DocumentPath=sch\sfp+.Harness
AnnotationEnabled=1
AnnotateStartValue=1
......@@ -768,7 +785,7 @@ DItemRevisionGUID=
GenerateClassCluster=0
DocumentUniqueId=
[Document44]
[Document45]
DocumentPath=sch\power-supply-2.Harness
AnnotationEnabled=1
AnnotateStartValue=1
......@@ -785,7 +802,7 @@ DItemRevisionGUID=
GenerateClassCluster=0
DocumentUniqueId=
[Document45]
[Document46]
DocumentPath=sch\fpga-bank-27-28.Harness
AnnotationEnabled=1
AnnotateStartValue=1
......@@ -802,7 +819,7 @@ DItemRevisionGUID=
GenerateClassCluster=0
DocumentUniqueId=
[Document46]
[Document47]
DocumentPath=sch\fpga-bank-65-66-67-68.Harness
AnnotationEnabled=1
AnnotateStartValue=1
......@@ -819,7 +836,7 @@ DItemRevisionGUID=
GenerateClassCluster=0
DocumentUniqueId=
[Document47]
[Document48]
DocumentPath=sch\fpga-bank-63.Harness
AnnotationEnabled=1
AnnotateStartValue=1
......@@ -836,7 +853,7 @@ DItemRevisionGUID=
GenerateClassCluster=0
DocumentUniqueId=
[Document48]
[Document49]
DocumentPath=sch\ddr4-pl.Harness
AnnotationEnabled=1
AnnotateStartValue=1
......@@ -853,7 +870,7 @@ DItemRevisionGUID=
GenerateClassCluster=0
DocumentUniqueId=
[Document49]
[Document50]
DocumentPath=sch\CLK_buffer_DRTIO_CDR.Harness
AnnotationEnabled=1
AnnotateStartValue=1
......@@ -870,7 +887,7 @@ DItemRevisionGUID=
GenerateClassCluster=0
DocumentUniqueId=
[Document50]
[Document51]
DocumentPath=sch\fpga-ps-mio.Harness
AnnotationEnabled=1
AnnotateStartValue=1
......@@ -887,6 +904,23 @@ DItemRevisionGUID=
GenerateClassCluster=0
DocumentUniqueId=
[Document52]
DocumentPath=DIOT_System_Board.OutJob
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None
DItemRevisionGUID=
GenerateClassCluster=0
DocumentUniqueId=
[ProjectVariant1]
UniqueID=8697C2F2-7DC8-47CA-8845-9A0327CC4A38
Description=Standard
......
hw/SIM/power_budget.ltp3 0 → 100644
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hw/fpga_pin_delays.csv 0 → 100644
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hw/sch/CLK_buffer_DRTIO_CDR.SchDoc.Harness 0 → 100644
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CLK_DIFF=CLK_P,CLK_N
PE_CLK=1_PE_CLK_P,1_PE_CLK_N,2_PE_CLK_P,2_PE_CLK_N,3_PE_CLK_P,3_PE_CLK_N,4_PE_CLK_P,4_PE_CLK_N,5_PE_CLK_P,5_PE_CLK_N,6_PE_CLK_P,6_PE_CLK_N,7_PE_CLK_P,7_PE_CLK_N,8_PE_CLK_P,8_PE_CLK_N
hw/sch/WR-clocks.SchDoc
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hw/sch/clocks.SchDoc
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hw/sch/fpga-bank-27.Harness 0 → 100644
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FMC_L=LA_P[33..0],LA_N[33..0],CLK_M2C_P[1..0],CLK_M2C_N[1..0],CLK_BIDIR_P[3..2],CLK_BIDIR_N[3..2],CLK_DIR,VREFA_M2C
hw/sch/fpga-bank-28.Harness 0 → 100644
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FMC_L=LA_P[33..0],LA_N[33..0],CLK_M2C_P[1..0],CLK_M2C_N[1..0],CLK_BIDIR_P[3..2],CLK_BIDIR_N[3..2],CLK_DIR,VREFA_M2C
hw/sch/fpga-power.SchDoc
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hw/sch/md5 0 → 100644
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480977e44e324f9c0cad3ac4081a9fa0 CLK_buffer_DRTIO_CDR.Harness
1cc42710ff97f0579f07bbab98b2250a CLK_buffer_DRTIO_CDR.SchDoc
e35a0429814e7bbf50798beb66354820 CLK_buffer_DRTIO_CDR.SchDoc.Harness
8c1e23919a9ca2ec1019dbd2af5d5124 clocks.Harness
9198968ce3de07f33cac7f912f29ec5c clocks.SchDoc
1f1a86436b80cbbb8ad051b1583d953f Cpcis_connectors_P1_P2_P3.Harness
299818a77b5981af97679b6ea626248e Cpcis_connectors_P1_P2_P3.SchDoc
97bebfa983f204e37898fdec20fd7730 Cpcis_connectors_P4_P5_P6.Harness
f0f7c1da10da6a6eae609614c2f4e599 Cpcis_connectors_P4_P5_P6.SchDoc
05f16d50ad09e630db8778b6beba9ca5 ddr4-pl.Harness
f4bacf28bb8fe0d7b8743a399a9db7b9 ddr4-pl.SchDoc
75885f0a804cae5fe1680137117a6276 ddr4-ps.Harness
5ae3a9e0445a130e6ae09d476d8f8692 ddr4-ps.SchDoc
2be6bea10b5c722224bfeaa1110018b3 DIOT_System_Board.SchDoc
ae8a29b3765ef25b8fee5f245e39297b fan-mon.Harness
5c7f0246a936269ae36ffef7aa2fa921 fan-mon.SchDoc
fc1160c0e02754ce3351af057bd29b46 flash.Harness
ee43846df72ad5adf0d5a0d5e57c1200 flash.SchDoc
40d2eb0da113f71fa6c9fee31643e88a fmc-connector.Harness
cbfa961db68e1f713f5ccff981879fec fmc-connector.SchDoc
3595c41d09480787ced02a2582aa0861 fpga-bank-27-28.Harness
42e3ab0d90446dffd137ea08a587fbb6 fpga-bank-27-28.SchDoc
35300a10e64715e968a9c798e47db6be fpga-bank-27.Harness
35300a10e64715e968a9c798e47db6be fpga-bank-28.Harness
626a15ad963d2357dd4375870da82c9e fpga-bank-63.Harness
f9e82a08aefadbdc94727ff836df91ef fpga-bank-63.SchDoc
62e4da1e6f81720e2f6c5c0203592470 fpga-bank-64.SchDoc
dc4dd380d45b3e778657a07e6dad06d2 fpga-bank-65-66-67-68.Harness
da5a36db1f988a64b135f9e987631ffa fpga-bank-65-66-67-68.SchDoc
ecbf7727d02ed1304f32ab1e0346ad7f fpga-bank-87-88.Harness
53235d6d2620ff985eef05b5eae82b1f fpga-bank-87-88.SchDoc
5c6360fe84c54fb33efe0bede9dc15fb fpga-config.SchDoc
27265d8c47ac1a66639b1473f8d9cdef fpga-mgts-power.SchDoc
065eb817941bd5ca73af1ba711811014 fpga-pl-mgts.Harness
7d01cd124ec6373ca8d7a38438e44fb1 fpga-pl-mgts.SchDoc
787162086593d16f5a7c48a8691f79f0 fpga-power.SchDoc
6c353f04abeedffc6435e8d9f2f2b0c7 fpga-ps-ddr4.SchDoc
c1fd7f8a89b7f2b8a6f1c62dddede231 fpga-ps-mgts.SchDoc
ae8a29b3765ef25b8fee5f245e39297b fpga-ps-mio.Harness
ca102aab3dd522ba8c5568f3decc79fb fpga-ps-mio.SchDoc
ae8a29b3765ef25b8fee5f245e39297b i2c_mux.Harness
6f66b868f6c8d9eb5c2d61371b1eec40 i2c_mux.SchDoc
c5c4889cb443ec83291e7e3bd861402b power-supply-1.Harness
49eaca9a0b07200260e715f8798b430d power-supply-1.SchDoc
c5c4889cb443ec83291e7e3bd861402b power-supply-2.Harness
e4230640ff78033fc0b34a181538ad20 power-supply-2.SchDoc
446453fac44ec88f771d62a89bd29e9a power-supply-3.SchDoc
3412ea7052936920106c7504a282d9d0 pxie_connector.Harness
1d013d04647ba6f14770fd03fda7e4f2 sfp+.Harness
735a89c0a3253b9840d8e809ca085c6d sfp+.SchDoc
dcc1d035772ee45bf16ed41a536b15e7 user_interface.SchDoc
8afb378de9b4315f9e79c19e6d320d19 WR-clocks.Harness
fb2e46ea43c10b58fb053e55b1f06cdd WR-clocks.SchDoc
hw/sch/sfp+.SchDoc
View file @ 03549333
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