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DIOT Igloo2-based radiation-tolerant System Board
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DIOT Igloo2-based radiation-tolerant System Board
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FPGA_Banks_1_2: add a note next to Bank1 saying it cannot handle LVDS therefore swapping signals with other banks shall be avoided
#66
· opened
Nov 16, 2020
by
Grzegorz Daniluk
sch v1.0
cosmetics
CLOSED
3
updated
Nov 16, 2020
FPGA_Banks_6_7: serdes Tx/Rx shall be AC-coupled
#28
· opened
Oct 27, 2020
by
Grzegorz Daniluk
sch v1.0
critical
CLOSED
1
updated
Nov 03, 2020
Issues on TPS7A (IC5 and IC4)
#46
· opened
Nov 05, 2020
by
Spyridon Georgakakis
sch v1.0
minor
CLOSED
1
updated
Nov 10, 2020
12V input power connector
#15
· opened
Oct 23, 2020
by
Paul PERONNARD
sch v1.0
minor
CLOSED
3
updated
Nov 03, 2020
Colouring of harness, wires, comments should take into account accessibility for color vision deficiency
#41
· opened
Nov 05, 2020
by
Spyridon Georgakakis
sch v1.0
cosmetics
CLOSED
4
updated
Dec 03, 2020
FPGA decoupling capacitors on dedicated sheet
#8
· opened
Oct 23, 2020
by
Paul PERONNARD
sch v1.0
cosmetics
CLOSED
1
updated
Nov 03, 2020
P12V fuse
#14
· opened
Oct 23, 2020
by
Paul PERONNARD
sch v1.0
critical
CLOSED
1
updated
Nov 05, 2020
Missing pull ups on TMS and TDI lines
#52
· opened
Nov 05, 2020
by
Spyridon Georgakakis
sch v1.0
minor
CLOSED
4
updated
Nov 10, 2020
FPGA pin U16 should be connected on Brown out circuit.
#49
· opened
Nov 05, 2020
by
Spyridon Georgakakis
sch v1.0
critical
CLOSED
1
updated
Nov 05, 2020
FMC net naming does not follow _P _N naming convention
#47
· opened
Nov 05, 2020
by
Spyridon Georgakakis
sch v1.0
cosmetics
CLOSED
3
updated
Nov 10, 2020
According to UG0451 the VPUMP pin should be left open at the JTAG connector
#59
· opened
Nov 06, 2020
by
Christos Gentsos
sch v1.0
critical
CLOSED
0
updated
Nov 06, 2020
Constrain_Periph_Nets: length matching for LVDS_17 quite loose
#67
· opened
Nov 16, 2020
by
Grzegorz Daniluk
sch v1.0
minor
CLOSED
2
updated
Nov 16, 2020
Missing pull resistors on SN74LVC2T45
#53
· opened
Nov 05, 2020
by
Spyridon Georgakakis
sch v1.0
minor
CLOSED
5
updated
Nov 11, 2020
FPGA Pin D24 is not an I/O.
#48
· opened
Nov 05, 2020
by
Spyridon Georgakakis
sch v1.0
cosmetics
CLOSED
2
updated
Nov 12, 2020
What is the startegy for current sense and voltage monitoring?
#54
· opened
Nov 05, 2020
by
Spyridon Georgakakis
sch v1.0
question
CLOSED
2
updated
Nov 09, 2020
I'd add I2C/SPI I/O expander to encode with resistor net version of the board and some unique ID chip.
#33
· opened
Oct 27, 2020
by
Grzegorz Daniluk
sch v1.0
minor
CLOSED
0
updated
Nov 11, 2020
FPGA_Bank1 cannot be used with LVDS signals, only single-ended or SSTL
#20
· opened
Oct 23, 2020
by
Grzegorz Daniluk
sch v1.0
critical
CLOSED
2
updated
Nov 09, 2020
IC14 analog domain issues
#57
· opened
Nov 05, 2020
by
Spyridon Georgakakis
sch v1.0
minor
CLOSED
2
updated
Nov 12, 2020
R6 and R7 on the Input of LT3083 (IC2)
#58
· opened
Nov 05, 2020
by
Spyridon Georgakakis
sch v1.0
critical
CLOSED
1
updated
Nov 05, 2020
IC6: TPS7A4533 Does not have enough copper at Pad 6 for heat dissipation.
#100
· opened
May 17, 2021
by
Spyridon Georgakakis
layout v1.0
minor
CLOSED
1
updated
May 17, 2021
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