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DIOT Igloo2-based radiation-tolerant System Board
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DIOT Igloo2-based radiation-tolerant System Board
Issues
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7
Closed
167
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174
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Height of components on bottom layer
#121
· opened
May 18, 2021
by
Spyridon Georgakakis
improvement
CLOSED
2
updated
Jan 10, 2023
add de-latching circuit to monitor FPGA core current
#126
· opened
Sep 21, 2021
by
Grzegorz Daniluk
improvement
CLOSED
3
updated
Jan 10, 2023
investigate adding current limiter for FPGA core to prevent destructive SELs
#127
· opened
Sep 21, 2021
by
Grzegorz Daniluk
improvement
CLOSED
2
updated
Jan 10, 2023
Add a 3 pin header to connect a UART for debugging
#130
· opened
Sep 29, 2021
by
Tristan Gingold
improvement
CLOSED
2
updated
Jan 10, 2023
Triplicate clock input
#132
· opened
Oct 05, 2021
by
Tristan Gingold
improvement
CLOSED
4
updated
Jan 10, 2023
bpolV12-board-swap-voltages
#145
· opened
Nov 17, 2022
by
Alén Arias Vázquez
CLOSED
0
updated
Jan 10, 2023
Fix OD_2V5C and OD_2V5D net labels
#129
· opened
Sep 29, 2021
by
Tristan Gingold
cosmetics
CLOSED
2
updated
Dec 01, 2022
No stock for some components, can we replace them?
3 of 3 tasks completed
#74
· opened
Mar 26, 2021
by
Grzegorz Daniluk
layout v1.0
critical
CLOSED
10
updated
Nov 17, 2022
reduce track length on decoupling capacitors
#82
· opened
May 04, 2021
by
Paul PERONNARD
layout v1.0
CLOSED
0
updated
May 25, 2021
relief connect on power smd components
#78
· opened
May 04, 2021
by
Paul PERONNARD
layout v1.0
CLOSED
3
updated
May 25, 2021
Vias sharing and decoupling caps net width
#108
· opened
May 17, 2021
by
Spyridon Georgakakis
layout v1.0
CLOSED
1
updated
May 21, 2021
Routing of VDDPLL and PLLVSSA should be done with Planes not traces
#106
· opened
May 17, 2021
by
Spyridon Georgakakis
layout v1.0
CLOSED
0
updated
May 21, 2021
LC filter layout can be improved
#123
· opened
May 21, 2021
by
Christos Gentsos
layout v1.0
minor
CLOSED
0
updated
May 21, 2021
P2V5_A rail is unused, it has to be removed
#122
· opened
May 20, 2021
by
Christos Gentsos
layout v1.0
minor
CLOSED
0
updated
May 21, 2021
Analog power filtering area
#101
· opened
May 17, 2021
by
Spyridon Georgakakis
layout v1.0
CLOSED
1
updated
May 21, 2021
IC20 and IC34 : TPS7A4901 Layout guidelines are not respected
#99
· opened
May 17, 2021
by
Spyridon Georgakakis
layout v1.0
CLOSED
0
updated
May 20, 2021
Placement of SERDES resistor and decoupling cap.
#110
· opened
May 17, 2021
by
Spyridon Georgakakis
layout v1.0
CLOSED
0
updated
May 19, 2021
L1: missing exposed GND plane between backplane P3 and P4 connectors
#94
· opened
May 10, 2021
by
Grzegorz Daniluk
layout v1.0
CLOSED
0
updated
May 19, 2021
MONIMOD I2C lines close to monitoring signals
#114
· opened
May 17, 2021
by
Spyridon Georgakakis
layout v1.0
CLOSED
0
updated
May 19, 2021
Board guide
#118
· opened
May 17, 2021
by
Spyridon Georgakakis
layout v1.0
CLOSED
1
updated
May 19, 2021
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