Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
DIOT Igloo2-based radiation-tolerant System Board
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
3
Issues
3
List
Board
Labels
Milestones
Merge Requests
1
Merge Requests
1
CI / CD
CI / CD
Pipelines
Jobs
Schedules
Charts
Wiki
Wiki
Snippets
Snippets
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Jobs
Commits
Issue Boards
Open sidebar
Projects
DIOT Igloo2-based radiation-tolerant System Board
Issues
Open
3
Closed
171
All
174
New issue
Recent searches
Press Enter or click to search
{{hint}}
{{tag}}
{{name}}
@{{username}}
No Assignee
{{name}}
@{{username}}
No Milestone
Upcoming
Started
{{title}}
No Label
{{title}}
{{name}}
Yes
No
Due date
Priority
Created date
Last updated
Milestone
Due date
Popularity
Label priority
Powering: replace jumper for PPERIPH selection with 0R resistors. P2V5 selected by default
#150
· opened
Jan 24, 2023
by
Grzegorz Daniluk
v2.0
Done
CLOSED
4
updated
Jan 24, 2023
Avoid 4-way connections in the schematic
#155
· opened
Feb 13, 2023
by
Grzegorz Daniluk
v2.0
Done
Schematic
CLOSED
1
updated
Feb 15, 2023
Bpol12V Solder mask layer
#161
· opened
Mar 24, 2023
by
Alén Arias Vázquez
v2.0
Layout
CLOSED
0
updated
Apr 18, 2023
move P2V5_PLL_VSSA polygon to L10 and expand CPCIS_12V polygon around J21
#165
· opened
Apr 04, 2023
by
Grzegorz Daniluk
v2.0
CLOSED
0
updated
Apr 04, 2023
relicense to CERN-OHL-W v2
#32
· opened
Oct 27, 2020
by
Grzegorz Daniluk
sch v1.0
cosmetics
CLOSED
0
updated
Oct 27, 2020
Go through the design checklist in AC393
#22
· opened
Oct 23, 2020
by
Christos Gentsos
sch v1.0
critical
CLOSED
1
updated
Nov 13, 2020
Translate_2V5_to_PPERIPH: SERVMOD_DIR pulled-up multiple times
#63
· opened
Nov 13, 2020
by
Grzegorz Daniluk
sch v1.0
minor
CLOSED
1
updated
Nov 13, 2020
Connect DEVRST_N to PGOOD.P1V2
#24
· opened
Oct 23, 2020
by
Christos Gentsos
sch v1.0
critical
CLOSED
0
updated
Nov 05, 2020
P connectors index should also include what is decided to be used within DIOT functionality
#42
· opened
Nov 05, 2020
by
Spyridon Georgakakis
sch v1.0
cosmetics
CLOSED
3
updated
Nov 11, 2020
Missing return vias (GND Vias) on serdes signals
#111
· opened
May 17, 2021
by
Spyridon Georgakakis
layout v1.0
CLOSED
1
updated
May 17, 2021
Maybe add a Power-up sequence diagram?
#40
· opened
Nov 05, 2020
by
Spyridon Georgakakis
sch v1.0
cosmetics
CLOSED
0
updated
Nov 10, 2020
Translate_2V5_to_PPERIPH: SHARED_BUS0..4 shall be puled up on System Board so that they can be used as multi-drop lines e.g. for IRQs
#64
· opened
Nov 13, 2020
by
Grzegorz Daniluk
sch v1.0
CLOSED
0
updated
Nov 13, 2020
Top_Misc: R171 should be not mounted
#65
· opened
Nov 13, 2020
by
Grzegorz Daniluk
sch v1.0
CLOSED
0
updated
Nov 13, 2020
Net Identifier scope and Hierarcy
#35
· opened
Nov 05, 2020
by
Spyridon Georgakakis
sch v1.0
cosmetics
CLOSED
2
updated
Dec 03, 2020
Use one sheet symbol and schematic for each connector and/or FPGA Banks
#37
· opened
Nov 05, 2020
by
Spyridon Georgakakis
sch v1.0
cosmetics
CLOSED
2
updated
Nov 10, 2020
current sense opamps
#12
· opened
Oct 23, 2020
by
Paul PERONNARD
sch v1.0
minor
CLOSED
2
updated
Nov 05, 2020
add de-latching circuit to monitor FPGA core current
#126
· opened
Sep 21, 2021
by
Grzegorz Daniluk
improvement
CLOSED
3
updated
Jan 10, 2023
FPGA_Banks_6_7: connecting FMC clocks
#30
· opened
Oct 27, 2020
by
Grzegorz Daniluk
sch v1.0
question
CLOSED
1
updated
Nov 10, 2020
L1 Common mode choke connection is not ok
#98
· opened
May 17, 2021
by
Spyridon Georgakakis
layout v1.0
CLOSED
0
updated
May 17, 2021
IC6: TPS7A4533 Does not have enough copper at Pad 6 for heat dissipation.
#100
· opened
May 17, 2021
by
Spyridon Georgakakis
layout v1.0
minor
CLOSED
1
updated
May 17, 2021
« First
Prev
1
2
3
4
5
6
…
Next
Last »