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DIOT Igloo2-based radiation-tolerant System Board
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DIOT Igloo2-based radiation-tolerant System Board
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Wrong pull ups at voltage translators (IC7)
#69
· opened
Dec 14, 2020
by
Volker Schramm
layout v1.0
Dec 18, 2020
critical
CLOSED
2
updated
Jan 28, 2021
L4 (X:192mm Y:54mm) P3V3 plane unnecessairly cuts into PPERIPH plane and therefore cuts plane below L3 signals
#92
· opened
May 07, 2021
by
Grzegorz Daniluk
layout v1.0
critical
CLOSED
0
updated
May 18, 2021
12V from the backplane connector could use more copper
#90
· opened
May 07, 2021
by
Grzegorz Daniluk
layout v1.0
critical
CLOSED
0
updated
May 18, 2021
No stock for some components, can we replace them?
3 of 3 tasks completed
#74
· opened
Mar 26, 2021
by
Grzegorz Daniluk
layout v1.0
critical
CLOSED
10
updated
Nov 17, 2022
Replace MURATA DLW5BSN191SQ2L (L1) with DLW5BSM191SQ2L
#73
· opened
Mar 26, 2021
by
Grzegorz Daniluk
v2.0
critical
Done
CLOSED
8
updated
Jan 26, 2023
IC6: missing input voltage
#72
· opened
Mar 16, 2021
by
Grzegorz Daniluk
layout v1.0
critical
CLOSED
1
updated
Apr 01, 2021
JTAG pull-ups and pull-downs
#71
· opened
Feb 04, 2021
by
Christos Gentsos
layout v1.0
critical
CLOSED
1
updated
Apr 01, 2021
Power Bank 2 with 3.3V and get rid of a bunch of level shifters
#61
· opened
Nov 11, 2020
by
Christos Gentsos
sch v1.0
critical
CLOSED
1
updated
Nov 11, 2020
According to UG0451 the VPUMP pin should be left open at the JTAG connector
#59
· opened
Nov 06, 2020
by
Christos Gentsos
sch v1.0
critical
CLOSED
0
updated
Nov 06, 2020
FPGA pin U16 should be connected on Brown out circuit.
#49
· opened
Nov 05, 2020
by
Spyridon Georgakakis
sch v1.0
critical
CLOSED
1
updated
Nov 05, 2020
R6 and R7 on the Input of LT3083 (IC2)
#58
· opened
Nov 05, 2020
by
Spyridon Georgakakis
sch v1.0
critical
CLOSED
1
updated
Nov 05, 2020
FPGA_Banks_6_7: serdes Tx/Rx shall be AC-coupled
#28
· opened
Oct 27, 2020
by
Grzegorz Daniluk
sch v1.0
critical
CLOSED
1
updated
Nov 03, 2020
Monitoring: ATSAMD21G18 is known to freeze in radiation, we should also have a power cycle/reset line from FPGA
#26
· opened
Oct 26, 2020
by
Grzegorz Daniluk
sch v1.0
critical
CLOSED
5
updated
Nov 12, 2020
Connect DEVRST_N to PGOOD.P1V2
#24
· opened
Oct 23, 2020
by
Christos Gentsos
sch v1.0
critical
CLOSED
0
updated
Nov 05, 2020
Fix JTAG pull-down and DEVRST_N pull-up values
#23
· opened
Oct 23, 2020
by
Christos Gentsos
sch v1.0
critical
CLOSED
1
updated
Nov 03, 2020
Harness type
#7
· opened
Oct 23, 2020
by
Paul PERONNARD
sch v1.0
critical
CLOSED
0
updated
Nov 03, 2020
Go through the design checklist in AC393
#22
· opened
Oct 23, 2020
by
Christos Gentsos
sch v1.0
critical
CLOSED
1
updated
Nov 13, 2020
power cycle pulse generator
#9
· opened
Oct 23, 2020
by
Paul PERONNARD
v2.0
critical
Done
Schematic
CLOSED
13
updated
Feb 15, 2023
P12V fuse
#14
· opened
Oct 23, 2020
by
Paul PERONNARD
sch v1.0
critical
CLOSED
1
updated
Nov 05, 2020
FPGA_Bank1 cannot be used with LVDS signals, only single-ended or SSTL
#20
· opened
Oct 23, 2020
by
Grzegorz Daniluk
sch v1.0
critical
CLOSED
2
updated
Nov 09, 2020
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