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DIOT Igloo2-based radiation-tolerant System Board
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DIOT Igloo2-based radiation-tolerant System Board
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FPGA Pin D24 is not an I/O.
#48
· opened
Nov 05, 2020
by
Spyridon Georgakakis
sch v1.0
cosmetics
CLOSED
2
updated
Nov 12, 2020
I'd add I2C/SPI I/O expander to encode with resistor net version of the board and some unique ID chip.
#33
· opened
Oct 27, 2020
by
Grzegorz Daniluk
sch v1.0
minor
CLOSED
0
updated
Nov 11, 2020
Power Bank 2 with 3.3V and get rid of a bunch of level shifters
#61
· opened
Nov 11, 2020
by
Christos Gentsos
sch v1.0
critical
CLOSED
1
updated
Nov 11, 2020
Translate_GPIO_to_2V5: more uniform translation circuits
#27
· opened
Oct 27, 2020
by
Grzegorz Daniluk
sch v1.0
minor
CLOSED
3
updated
Nov 11, 2020
Add a pin header for a possible monitoring expansion board
#60
· opened
Nov 11, 2020
by
Christos Gentsos
sch v1.0
minor
CLOSED
0
updated
Nov 11, 2020
Missing pull resistors on SN74LVC2T45
#53
· opened
Nov 05, 2020
by
Spyridon Georgakakis
sch v1.0
minor
CLOSED
5
updated
Nov 11, 2020
aligning net labels
#31
· opened
Oct 27, 2020
by
Grzegorz Daniluk
sch v1.0
cosmetics
CLOSED
1
updated
Nov 11, 2020
P connectors index should also include what is decided to be used within DIOT functionality
#42
· opened
Nov 05, 2020
by
Spyridon Georgakakis
sch v1.0
cosmetics
CLOSED
3
updated
Nov 11, 2020
2 types of 10uF Capacitors
#45
· opened
Nov 05, 2020
by
Spyridon Georgakakis
sch v1.0
minor
CLOSED
2
updated
Nov 10, 2020
Unify harness representation in schematics
#36
· opened
Nov 05, 2020
by
Spyridon Georgakakis
sch v1.0
cosmetics
CLOSED
0
updated
Nov 10, 2020
Use one sheet symbol and schematic for each connector and/or FPGA Banks
#37
· opened
Nov 05, 2020
by
Spyridon Georgakakis
sch v1.0
cosmetics
CLOSED
2
updated
Nov 10, 2020
Maybe add a Power-up sequence diagram?
#40
· opened
Nov 05, 2020
by
Spyridon Georgakakis
sch v1.0
cosmetics
CLOSED
0
updated
Nov 10, 2020
FMC net naming does not follow _P _N naming convention
#47
· opened
Nov 05, 2020
by
Spyridon Georgakakis
sch v1.0
cosmetics
CLOSED
3
updated
Nov 10, 2020
Issues on TPS7A (IC5 and IC4)
#46
· opened
Nov 05, 2020
by
Spyridon Georgakakis
sch v1.0
minor
CLOSED
1
updated
Nov 10, 2020
Missing pull ups on TMS and TDI lines
#52
· opened
Nov 05, 2020
by
Spyridon Georgakakis
sch v1.0
minor
CLOSED
4
updated
Nov 10, 2020
FPGA_Banks_6_7: connecting FMC clocks
#30
· opened
Oct 27, 2020
by
Grzegorz Daniluk
sch v1.0
question
CLOSED
1
updated
Nov 10, 2020
Jtag Chain needs a block diagram for visualization
#39
· opened
Nov 05, 2020
by
Spyridon Georgakakis
sch v1.0
cosmetics
CLOSED
5
updated
Nov 10, 2020
Does FEAST need filtering to comply with EN 55022 class a or b directives?
#55
· opened
Nov 05, 2020
by
Spyridon Georgakakis
sch v1.0
question
CLOSED
3
updated
Nov 10, 2020
FPGA_Bank1 cannot be used with LVDS signals, only single-ended or SSTL
#20
· opened
Oct 23, 2020
by
Grzegorz Daniluk
sch v1.0
critical
CLOSED
2
updated
Nov 09, 2020
What is the startegy for current sense and voltage monitoring?
#54
· opened
Nov 05, 2020
by
Spyridon Georgakakis
sch v1.0
question
CLOSED
2
updated
Nov 09, 2020
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