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DIOT Kintex Ultrascale-based Peripheral Board FMC Carrier
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DIOT Kintex Ultrascale-based Peripheral Board FMC Carrier
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1
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62
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External DIO
#5
· opened
Oct 30, 2020
by
Paul PERONNARD
sch v1.0
Done
major
CLOSED
5
updated
Sep 06, 2021
ESD strips and nets are floating.
#27
· opened
Nov 05, 2020
by
Spyridon Georgakakis
sch v1.0
Done
minor
CLOSED
1
updated
Jul 05, 2021
JTAG lines pull resistors
#31
· opened
Nov 05, 2020
by
Spyridon Georgakakis
sch v1.0
Done
major
CLOSED
6
updated
Mar 25, 2021
JTAG functionality
#33
· opened
Nov 05, 2020
by
Spyridon Georgakakis
sch v1.0
minor
question
CLOSED
4
updated
Feb 04, 2021
Explanatory heading is missing from some design schematic pages.
#13
· opened
Nov 05, 2020
by
Spyridon Georgakakis
sch v1.0
minor
CLOSED
3
updated
Feb 04, 2021
Is a Power-up sequence diagram needed?
#17
· opened
Nov 05, 2020
by
Spyridon Georgakakis
sch v1.0
Done
question
CLOSED
7
updated
Feb 04, 2021
CERN OHL Licence should be -W instead of -S
#35
· opened
Nov 12, 2020
by
Erik van der Bij
sch v1.0
Done
minor
CLOSED
1
updated
Feb 04, 2021
FPGA_Bank_44_64_65: LED_USER0 could be moved to Bank44
#73
· opened
Jan 28, 2021
by
Grzegorz Daniluk
sch v1.0
Done
minor
CLOSED
0
updated
Feb 04, 2021
CPCIS_Connectors_P1_P4_P6: Fix JTAG lines assignment to BP_DUAL diff pairs
3 of 5 tasks completed
#74
· opened
Jan 28, 2021
by
Grzegorz Daniluk
sch v1.0
Done
major
CLOSED
0
updated
Feb 04, 2021
CPCIS_Connectors_P1_P4_P6: BP_DUAL and BP_IO LVDS diff pairs numbering shall reflect the cross-over in the backplane
#55
· opened
Nov 20, 2020
by
Grzegorz Daniluk
sch v1.0
Done
minor
CLOSED
3
updated
Jan 28, 2021
P connectors index/legend should also include what is decided to be used within DIOT functionality
#18
· opened
Nov 05, 2020
by
Spyridon Georgakakis
sch v1.0
Done
minor
CLOSED
2
updated
Jan 28, 2021
Optimise bill-of-materials
10 of 10 tasks completed
#71
· opened
Dec 03, 2020
by
Grzegorz Daniluk
sch v1.0
Done
minor
CLOSED
1
updated
Jan 28, 2021
Connect SERVMOD also to FPGA pin
#70
· opened
Dec 02, 2020
by
Grzegorz Daniluk
sch v1.0
Done
major
CLOSED
1
updated
Jan 28, 2021
FPGA_Bank_44_64_65: BP_IO.LVDS_P/N_12 isn't connected to FPGA diff pair
#69
· opened
Dec 02, 2020
by
Grzegorz Daniluk
sch v1.0
Done
major
CLOSED
0
updated
Jan 28, 2021
USB_Quad and Power_Supply_3 could use the same LDO to produce 3V3 from 5V
#68
· opened
Dec 02, 2020
by
Grzegorz Daniluk
sch v1.0
Done
minor
CLOSED
1
updated
Jan 28, 2021
Re-annotate the whole schematics
#67
· opened
Dec 02, 2020
by
Grzegorz Daniluk
sch v1.0
Done
minor
CLOSED
4
updated
Jan 27, 2021
Add a startup oscillator that could be easily used before/instead programming Si5341
#66
· opened
Dec 02, 2020
by
Grzegorz Daniluk
sch v1.0
Done
major
CLOSED
4
updated
Jan 27, 2021
Sensors: why they are powered from P3V3_reg and not from P3V3?
#65
· opened
Dec 02, 2020
by
Grzegorz Daniluk
sch v1.0
Done
minor
CLOSED
3
updated
Jan 27, 2021
FPGA_BANK_66_67_68_DDR: random indentation of net labels?
#63
· opened
Nov 23, 2020
by
Grzegorz Daniluk
sch v1.0
Done
minor
CLOSED
0
updated
Jan 27, 2021
FPGA_Bank_44_64_65: rename UART signals
2 of 2 tasks completed
#61
· opened
Nov 23, 2020
by
Grzegorz Daniluk
sch v1.0
Done
minor
CLOSED
0
updated
Jan 27, 2021
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