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DIOT Kintex Ultrascale-based Peripheral Board FMC Carrier
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DIOT Kintex Ultrascale-based Peripheral Board FMC Carrier
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Increase clearance between traces and FMC mounting holes
#92
· opened
Jul 21, 2021
by
Grzegorz Daniluk
layout-v1.0
Done
major
CLOSED
1
updated
Sep 07, 2021
Some traces are very close to FPGA heatsink mounting holes
#91
· opened
Jul 21, 2021
by
Grzegorz Daniluk
layout-v1.0
Done
major
CLOSED
1
updated
Sep 07, 2021
DDR4 routing
#87
· opened
Jul 21, 2021
by
Paul PERONNARD
major
CLOSED
1
updated
Sep 07, 2021
236 DRC errors, mostly on length matching but also on front panel LEMO collision
#78
· opened
Jul 14, 2021
by
Grzegorz Daniluk
layout-v1.0
major
CLOSED
8
updated
Sep 24, 2021
Backplane MGT vs LVDS lanes routing
#77
· opened
Jul 07, 2021
by
Grzegorz Daniluk
layout-v1.0
Done
major
CLOSED
6
updated
Sep 07, 2021
[FPGA_Bank_66_67_68_DDR] forbidden I/O assignment
#76
· opened
Jul 06, 2021
by
Grzegorz Daniluk
layout-v1.0
major
CLOSED
1
updated
Jul 07, 2021
CPCIS_Connectors_P1_P4_P6: Fix JTAG lines assignment to BP_DUAL diff pairs
3 of 5 tasks completed
#74
· opened
Jan 28, 2021
by
Grzegorz Daniluk
sch v1.0
Done
major
CLOSED
0
updated
Feb 04, 2021
Connect SERVMOD also to FPGA pin
#70
· opened
Dec 02, 2020
by
Grzegorz Daniluk
sch v1.0
Done
major
CLOSED
1
updated
Jan 28, 2021
FPGA_Bank_44_64_65: BP_IO.LVDS_P/N_12 isn't connected to FPGA diff pair
#69
· opened
Dec 02, 2020
by
Grzegorz Daniluk
sch v1.0
Done
major
CLOSED
0
updated
Jan 28, 2021
Add a startup oscillator that could be easily used before/instead programming Si5341
#66
· opened
Dec 02, 2020
by
Grzegorz Daniluk
sch v1.0
Done
major
CLOSED
4
updated
Jan 27, 2021
FPGA_Bank_44_64_65: SD_DETECT missing pull-up
#60
· opened
Nov 23, 2020
by
Grzegorz Daniluk
sch v1.0
Done
major
CLOSED
1
updated
Jan 27, 2021
DDR4_SODIMM: VDDSPD should be P2V5
#57
· opened
Nov 23, 2020
by
Grzegorz Daniluk
sch v1.0
Done
major
CLOSED
0
updated
Jan 27, 2021
BP_IO.GA0..3 shall be pulled-up on this board
#56
· opened
Nov 20, 2020
by
Grzegorz Daniluk
sch v1.0
Done
major
CLOSED
2
updated
Jan 27, 2021
CPCIS_Connectors_P1_P4_P6: provide power to RTM
#52
· opened
Nov 20, 2020
by
Grzegorz Daniluk
sch v1.0
major
CLOSED
5
updated
Dec 16, 2020
CPCIS_Connectors_P1_P4_P6: voltage levels incompatibility at IC5/6/7
#50
· opened
Nov 19, 2020
by
Grzegorz Daniluk
sch v1.0
Done
major
CLOSED
7
updated
Jan 27, 2021
C156 is used above its voltage rating, C153 exactly on it
#48
· opened
Nov 18, 2020
by
Christos Gentsos
sch v1.0
Done
major
CLOSED
2
updated
Jan 27, 2021
R90 and R91 both 0 Ohm short power supplies. One should be "not mounted" (page 9)
#40
· opened
Nov 12, 2020
by
Erik van der Bij
sch v1.0
major
CLOSED
5
updated
Jan 06, 2021
R95 with R97 of 0 Ohm short P3V3 (page 5)
#38
· opened
Nov 12, 2020
by
Erik van der Bij
sch v1.0
major
CLOSED
4
updated
Jan 06, 2021
JTAG lines pull resistors
#31
· opened
Nov 05, 2020
by
Spyridon Georgakakis
sch v1.0
Done
major
CLOSED
6
updated
Mar 25, 2021
Error on SN74CB3T3257PW component design
#28
· opened
Nov 05, 2020
by
Spyridon Georgakakis
sch v1.0
Done
major
CLOSED
3
updated
Jan 27, 2021
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