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DIOT Kintex Ultrascale-based Peripheral Board FMC Carrier
DIOT Kintex Ultrascale-based Peripheral Board FMC Carrier
Commit 5423fb99 authored by Paweł's avatar Paweł
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Initial commit with schematics ready for review

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.gitignore 0 → 100644
View file @ 5423fb99
hw/History
hw/__Previews
hw/sch/__Previews
hw/Project*
*7z
*zip
hw/DIOT_FMC_Carrier.OutJob 0 → 100644
View file @ 5423fb99
[OutputJobFile]
Version=1.0
Caption=
Description=
VaultGUID=
ItemGUID=
ItemHRID=
RevisionGUID=
RevisionId=
VaultHRID=
AutoItemHRID=
NextRevId=
FolderGUID=
LifeCycleDefinitionGUID=
RevisionNamingSchemeGUID=
[OutputGroup1]
Name=Job1.OutJob
Description=
TargetOutputMedium=PDF
VariantName=Default
VariantScope=1
CurrentConfigurationName=
TargetPrinter=Virtual Printer
PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=0
OutputMedium1=Print Job
OutputMedium1_Type=Printer
OutputMedium1_Printer=
OutputMedium1_PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1
OutputMedium2=PDF
OutputMedium2_Type=Publish
OutputMedium3=Folder Structure
OutputMedium3_Type=GeneratedFiles
OutputMedium4=Video
OutputMedium4_Type=Multimedia
OutputType1=Schematic Print
OutputName1=Schematic Prints
OutputCategory1=Documentation
OutputDocumentPath1=[Project Physical Documents]
OutputVariantName1=
OutputEnabled1=1
OutputEnabled1_OutputMedium1=0
OutputEnabled1_OutputMedium2=1
OutputEnabled1_OutputMedium3=0
OutputEnabled1_OutputMedium4=0
OutputDefault1=0
PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=0|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
Configuration1_Name1=OutputConfigurationParameter1
Configuration1_Item1=Record=SchPrintView|ShowNoERC=True|ShowParamSet=True|ShowProbe=True|ShowBlanket=True|NoERCSymbolsToShow="Thin Cross","Thick Cross","Small Cross",Checkbox,Triangle|ShowNote=True|ShowNoteCollapsed=True|ShowOpenEnds=True|ExpandDesignator=True|ExpandNetLabel=False|ExpandPort=False|ExpandSheetNum=False|ExpandDocNum=False|PrintArea=0|PrintAreaRect.X1=0|PrintAreaRect.Y1=0|PrintAreaRect.X2=0|PrintAreaRect.Y2=0
[PublishSettings]
OutputFilePath2=.\Project Outputs for DIOT_FMC_Carrier\Free Documents.PDF
ReleaseManaged2=0
OutputBasePath2=.\Project Outputs for DIOT_FMC_Carrier\
OutputPathMedia2=
OutputPathMediaValue2=
OutputPathOutputer2=[Output Type]
OutputPathOutputerPrefix2=
OutputPathOutputerValue2=
OutputFileName2=Job1.PDF
OutputFileNameMulti2=
UseOutputNameForMulti2=0
OutputFileNameSpecial2==ProjectName
OpenOutput2=1
PromptOverwrite2=1
PublishMethod2=0
ZoomLevel2=50
FitSCHPrintSizeToDoc2=1
FitPCBPrintSizeToDoc2=1
GenerateNetsInfo2=1
MarkPins2=1
MarkNetLabels2=1
MarkPortsId2=1
GenerateTOC2=1
ShowComponentParameters2=1
GlobalBookmarks2=0
PDFACompliance2=Disabled
PDFVersion2=Default
OutputFilePath3=
ReleaseManaged3=1
OutputBasePath3=
OutputPathMedia3=
OutputPathMediaValue3=
OutputPathOutputer3=[Output Type]
OutputPathOutputerPrefix3=
OutputPathOutputerValue3=
OutputFileName3=
OutputFileNameMulti3=
UseOutputNameForMulti3=1
OutputFileNameSpecial3=
OpenOutput3=1
OutputFilePath4=
ReleaseManaged4=1
OutputBasePath4=
OutputPathMedia4=
OutputPathMediaValue4=
OutputPathOutputer4=[Output Type]
OutputPathOutputerPrefix4=
OutputPathOutputerValue4=
OutputFileName4=
OutputFileNameMulti4=
UseOutputNameForMulti4=1
OutputFileNameSpecial4=
OpenOutput4=1
PromptOverwrite4=1
PublishMethod4=5
ZoomLevel4=50
FitSCHPrintSizeToDoc4=1
FitPCBPrintSizeToDoc4=1
GenerateNetsInfo4=1
MarkPins4=1
MarkNetLabels4=1
MarkPortsId4=1
MediaFormat4=Windows Media file (*.wmv,*.wma,*.asf)
FixedDimensions4=1
Width4=352
Height4=288
MultiFile4=0
FramesPerSecond4=25
FramesPerSecondDenom4=1
AviPixelFormat4=7
AviCompression4=MP42 MS-MPEG4 V2
AviQuality4=100
FFmpegVideoCodecId4=13
FFmpegPixelFormat4=0
FFmpegQuality4=80
WmvVideoCodecName4=Windows Media Video V7
WmvQuality4=80
[GeneratedFilesSettings]
RelativeOutputPath2=.\Project Outputs for DIOT_FMC_Carrier\Free Documents.PDF
OpenOutputs2=1
RelativeOutputPath3=
OpenOutputs3=1
AddToProject3=1
TimestampFolder3=0
UseOutputName3=0
OpenODBOutput3=0
OpenGerberOutput3=0
OpenNCDrillOutput3=0
OpenIPCOutput3=0
EnableReload3=0
RelativeOutputPath4=
OpenOutputs4=1
hw/DIOT_FMC_Carrier.PrjPcb 0 → 100644
View file @ 5423fb99
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hw/DIOT_FMC_Carrier.PrjPcbStructure 0 → 100644
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Record=TopLevelDocument|FileName=DIOT_FMC_Carrier.SchDoc
Record=SheetSymbol|SourceDocument=DIOT_FMC_Carrier.SchDoc|Designator=U_Clocks|SchDesignator=U_Clocks|FileName=Clocks.SchDoc|SymbolType=Normal|RawFileName=Clocks.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=DIOT_FMC_Carrier.SchDoc|Designator=U_CPCIS_Connectors_P1_P4_P6|SchDesignator=U_CPCIS_Connectors_P1_P4_P6|FileName=CPCIS_Connectors_P1_P4_P6.SchDoc|SymbolType=Normal|RawFileName=CPCIS_Connectors_P1_P4_P6.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=DIOT_FMC_Carrier.SchDoc|Designator=U_DDR4_SODIMM|SchDesignator=U_DDR4_SODIMM|FileName=DDR4_SODIMM.schdoc|SymbolType=Normal|RawFileName=DDR4_SODIMM.schdoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=DIOT_FMC_Carrier.SchDoc|Designator=U_FMC_Connector|SchDesignator=U_FMC_Connector|FileName=FMC_Connector.SchDoc|SymbolType=Normal|RawFileName=FMC_Connector.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=DIOT_FMC_Carrier.SchDoc|Designator=U_FPGA_Bank_0_CFG|SchDesignator=U_FPGA_Bank_0_CFG|FileName=FPGA_Bank_0_CFG.SchDoc|SymbolType=Normal|RawFileName=FPGA_Bank_0_CFG.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=DIOT_FMC_Carrier.SchDoc|Designator=U_FPGA_Bank_44_64_65|SchDesignator=U_FPGA_Bank_44_64_65|FileName=FPGA_Bank_44_64_65.SchDoc|SymbolType=Normal|RawFileName=FPGA_Bank_44_64_65.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=DIOT_FMC_Carrier.SchDoc|Designator=U_FPGA_Bank_45-48_FMC|SchDesignator=U_FPGA_Bank_45-48_FMC|FileName=FPGA_Bank_45-48_FMC.SchDoc|SymbolType=Normal|RawFileName=FPGA_Bank_45-48_FMC.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=DIOT_FMC_Carrier.SchDoc|Designator=U_FPGA_Bank_66_67_68_DDR|SchDesignator=U_FPGA_Bank_66_67_68_DDR|FileName=FPGA_Bank_66_67_68_DDR.SchDoc|SymbolType=Normal|RawFileName=FPGA_Bank_66_67_68_DDR.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=DIOT_FMC_Carrier.SchDoc|Designator=U_FPGA_Bank_224-227_MGT|SchDesignator=U_FPGA_Bank_224-227_MGT|FileName=FPGA_Bank_224-227_MGT.SchDoc|SymbolType=Normal|RawFileName=FPGA_Bank_224-227_MGT.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=DIOT_FMC_Carrier.SchDoc|Designator=U_FPGA_Supplies|SchDesignator=U_FPGA_Supplies|FileName=FPGA_Supplies.SchDoc|SymbolType=Normal|RawFileName=FPGA_Supplies.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=DIOT_FMC_Carrier.SchDoc|Designator=U_Power_Supply_1|SchDesignator=U_Power_Supply_1|FileName=Power_Supply_1.SchDoc|SymbolType=Normal|RawFileName=Power_Supply_1.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=DIOT_FMC_Carrier.SchDoc|Designator=U_Power_Supply_2|SchDesignator=U_Power_Supply_2|FileName=Power_Supply_2.SchDoc|SymbolType=Normal|RawFileName=Power_Supply_2.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=DIOT_FMC_Carrier.SchDoc|Designator=U_Power_Supply_3|SchDesignator=U_Power_Supply_3|FileName=Power_Supply_3.SchDoc|SymbolType=Normal|RawFileName=Power_Supply_3.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=DIOT_FMC_Carrier.SchDoc|Designator=U_Sensors|SchDesignator=U_Sensors|FileName=Sensors.SchDoc|SymbolType=Normal|RawFileName=Sensors.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=DIOT_FMC_Carrier.SchDoc|Designator=U_USB_Quad|SchDesignator=U_USB_Quad|FileName=USB_Quad.SchDoc|SymbolType=Normal|RawFileName=USB_Quad.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
hw/sch/CPCIS_Connectors_P1_P4_P6.Harness 0 → 100644
View file @ 5423fb99
BP_Conn=LVDS_P[0..14],LVDS_N[0..14],SHARED_BUS_[0..4],GA[0..3]
BP_RTM=IO_P[0..22],IO_N[0..22],SHARED_BUS[0..7]
CLK_DIFF=CLK_P,CLK_N
I2C=SDA,SCL
JTAG5=TCK,TDI,TDO,TMS,TRSTn
MGT=Tx_P,Tx_N,Rx_P,Rx_N
hw/sch/Clocks.Harness 0 → 100644
View file @ 5423fb99
CDR_PLL_CTRL=Main_DCXO_SDA,Main_DCXO_SCL,Main_DCXO_OE,Helper_DCXO_OE,Helper_DCXO_SDA,Helper_DCXO_SCL
CLK_DIFF=CLK_P,CLK_N
I2C=SDA,SCL
MGT_CLKREF_H=CLK_P[1..0],CLK_N[1..0]
hw/sch/DDR4_SODIMM.Harness 0 → 100644
View file @ 5423fb99
DDR4_x64=CB[7..0],DQ[63..0],DM[8..0],DQS_P[8..0],DQS_N[8..0],A[16..0],CK_P[1..0],CK_N[1..0],CKE[1..0],RST_N,ACT_N,PAR,CS_N[3..0],ODT[1..0],BA[1..0],BG[1..0],ALERT_N,EVENT_n,{I2C:I2C}
hw/sch/FMC_Connector.Harness 0 → 100644
View file @ 5423fb99
CLK_DIFF=CLK_P,CLK_N
FMC=LA_P[0..33],LA_N[0..33],HA_P[0..23],HA_N[0..23],HB_P[0..21],HB_N[0..21],VREFA_M2C,VREFB_M2C,CLK_DIR
FMC_CLK=CLK_M2C_P[0..1],CLK_M2C_N[0..1],CLK_BIDIR_P[2..3],CLK_BIDIR_N[2..3]
FMC_MGT=GBTCLK_M2C_P[0..1],GBTCLK_M2C_N[0..1],DP_C2M_P[0..9],DP_C2M_N[0..9],DP_M2C_P[0..9],DP_M2C_N[0..9]
I2C=SDA,SCL
JTAG5=TCK,TDI,TDO,TMS,TRSTn
hw/sch/FPGA_Bank_0_CFG.Harness 0 → 100644
View file @ 5423fb99
FPGA_THERM=DXP,DXN
JTAG5=TCK,TDI,TDO,TMS,TRSTn
hw/sch/FPGA_Bank_224-227_MGT.Harness 0 → 100644
View file @ 5423fb99
FMC_MGT=DP_C2M_N[0..9],DP_C2M_P[0..9],DP_M2C_N[0..9],DP_M2C_P[0..9],GBTCLK_M2C_N[0..1],GBTCLK_M2C_P[0..1]
MGT=Rx_P,Rx_N,Tx_P,Tx_N
MGT_CLKREF_H=CLK_P[1..0],CLK_N[1..0]
hw/sch/FPGA_Bank_44_64_65.Harness 0 → 100644
View file @ 5423fb99
BP_Conn=GA[0..3],LVDS_P[0..14],LVDS_N[0..14],SHARED_BUS_[0..4]
BP_RTM=IO_P[0..22],IO_N[0..22],SHARED_BUS[0..7]
CDR_PLL_CTRL=Helper_DCXO_OE,Helper_DCXO_SCL,Helper_DCXO_SDA,Main_DCXO_OE,Main_DCXO_SCL,Main_DCXO_SDA
I2C=SDA,SCL
hw/sch/FPGA_Bank_45-48_FMC.Harness 0 → 100644
View file @ 5423fb99
CLK_DIFF=CLK_P,CLK_N
FMC=CLK_DIR,HA_N[0..23],HA_P[0..23],HB_N[0..21],HB_P[0..21],LA_N[0..33],LA_P[0..33],VREFA_M2C,VREFB_M2C
FMC_CLK=CLK_M2C_P[0..1],CLK_M2C_N[0..1],CLK_BIDIR_P[2..3],CLK_BIDIR_N[2..3]
hw/sch/FPGA_Bank_66_67_68_DDR.Harness 0 → 100644
View file @ 5423fb99
CLK_DIFF=CLK_P,CLK_N
DDR4_x64=CB[7..0],DQ[63..0],DM[8..0],DQS_P[8..0],DQS_N[8..0],A[16..0],CK_P[1..0],CK_N[1..0],CKE[1..0],RST_N,ACT_N,PAR,CS_N[3..0],ODT[1..0],BA[1..0],BG[1..0],ALERT_N,EVENT_n,{I2C:I2C}
hw/sch/Sensors.Harness 0 → 100644
View file @ 5423fb99
FPGA_THERM=DXP,DXN
I2C=SDA,SCL
hw/sch/USB_Quad.Harness 0 → 100644
View file @ 5423fb99
I2C=SDA,SCL
JTAG5=TDI,TCK,TMS,TDO,TRSTn
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