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DIOT Kintex Ultrascale-based Peripheral Board FMC Carrier
DIOT Kintex Ultrascale-based Peripheral Board FMC Carrier
Commit 40a04a07 authored by Pawel's avatar Pawel
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WIP on DDR4 simulations

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hw/DIOT_FMC_Carrier.OutJob
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hw/DIOT_FMC_Carrier.PrjPcb
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hw/DIOT_FMC_Carrier.PrjPcbStructure
View file @ 40a04a07
Record=TopLevelDocument|FileName=DIOT_FMC_Carrier.SchDoc|SheetNumber=1
Record=SheetSymbol|SourceDocument=DIOT_FMC_Carrier.SchDoc|Designator=U_Clocks|SchDesignator=U_Clocks|FileName=Clocks.SchDoc|SheetNumber=15|SymbolType=Normal|RawFileName=Clocks.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=DIOT_FMC_Carrier.SchDoc|Designator=U_CPCIS_Connectors_P1_P4_P6|SchDesignator=U_CPCIS_Connectors_P1_P4_P6|FileName=CPCIS_Connectors_P1_P4_P6.SchDoc|SheetNumber=10|SymbolType=Normal|RawFileName=CPCIS_Connectors_P1_P4_P6.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=DIOT_FMC_Carrier.SchDoc|Designator=U_DDR4_SODIMM|SchDesignator=U_DDR4_SODIMM|FileName=DDR4_SODIMM.schdoc|SheetNumber=3|SymbolType=Normal|RawFileName=DDR4_SODIMM.schdoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=DIOT_FMC_Carrier.SchDoc|Designator=U_FMC_Connector|SchDesignator=U_FMC_Connector|FileName=FMC_Connector.SchDoc|SheetNumber=2|SymbolType=Normal|RawFileName=FMC_Connector.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=DIOT_FMC_Carrier.SchDoc|Designator=U_FPGA_Bank_0_CFG|SchDesignator=U_FPGA_Bank_0_CFG|FileName=FPGA_Bank_0_CFG.SchDoc|SheetNumber=4|SymbolType=Normal|RawFileName=FPGA_Bank_0_CFG.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=DIOT_FMC_Carrier.SchDoc|Designator=U_FPGA_Bank_44-46_48_FMC|SchDesignator=U_FPGA_Bank_44-46_48_FMC|FileName=FPGA_Bank_44-46_48_FMC.SchDoc|SheetNumber=6|SymbolType=Normal|RawFileName=FPGA_Bank_44-46_48_FMC.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=DIOT_FMC_Carrier.SchDoc|Designator=U_FPGA_Bank_47_64_65|SchDesignator=U_FPGA_Bank_47_64_65|FileName=FPGA_Bank_47_64_65.SchDoc|SheetNumber=5|SymbolType=Normal|RawFileName=FPGA_Bank_47_64_65.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=DIOT_FMC_Carrier.SchDoc|Designator=U_FPGA_Bank_66_67_68_DDR|SchDesignator=U_FPGA_Bank_66_67_68_DDR|FileName=FPGA_Bank_66_67_68_DDR.SchDoc|SheetNumber=7|SymbolType=Normal|RawFileName=FPGA_Bank_66_67_68_DDR.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=DIOT_FMC_Carrier.SchDoc|Designator=U_FPGA_Bank_224-227_MGT|SchDesignator=U_FPGA_Bank_224-227_MGT|FileName=FPGA_Bank_224-227_MGT.SchDoc|SheetNumber=8|SymbolType=Normal|RawFileName=FPGA_Bank_224-227_MGT.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=DIOT_FMC_Carrier.SchDoc|Designator=U_FPGA_Supplies|SchDesignator=U_FPGA_Supplies|FileName=FPGA_Supplies.SchDoc|SheetNumber=9|SymbolType=Normal|RawFileName=FPGA_Supplies.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=DIOT_FMC_Carrier.SchDoc|Designator=U_Power_Supply_1|SchDesignator=U_Power_Supply_1|FileName=Power_Supply_1.SchDoc|SheetNumber=11|SymbolType=Normal|RawFileName=Power_Supply_1.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=DIOT_FMC_Carrier.SchDoc|Designator=U_Power_Supply_2|SchDesignator=U_Power_Supply_2|FileName=Power_Supply_2.SchDoc|SheetNumber=12|SymbolType=Normal|RawFileName=Power_Supply_2.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=DIOT_FMC_Carrier.SchDoc|Designator=U_Power_Supply_3|SchDesignator=U_Power_Supply_3|FileName=Power_Supply_3.SchDoc|SheetNumber=13|SymbolType=Normal|RawFileName=Power_Supply_3.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=DIOT_FMC_Carrier.SchDoc|Designator=U_Sensors|SchDesignator=U_Sensors|FileName=Sensors.SchDoc|SheetNumber=14|SymbolType=Normal|RawFileName=Sensors.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=DIOT_FMC_Carrier.SchDoc|Designator=U_USB_Quad|SchDesignator=U_USB_Quad|FileName=USB_Quad.SchDoc|SheetNumber=16|SymbolType=Normal|RawFileName=USB_Quad.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=TopLevelDocument|FileName=DIOT_FMC_Carrier.SchDoc|SheetNumber=1
Record=SheetSymbol|SourceDocument=DIOT_FMC_Carrier.SchDoc|Designator=U_Clocks|SchDesignator=U_Clocks|FileName=Clocks.SchDoc|SheetNumber=15|SymbolType=Normal|RawFileName=Clocks.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=DIOT_FMC_Carrier.SchDoc|Designator=U_CPCIS_Connectors_P1_P4_P6|SchDesignator=U_CPCIS_Connectors_P1_P4_P6|FileName=CPCIS_Connectors_P1_P4_P6.SchDoc|SheetNumber=10|SymbolType=Normal|RawFileName=CPCIS_Connectors_P1_P4_P6.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=DIOT_FMC_Carrier.SchDoc|Designator=U_DDR4_SODIMM|SchDesignator=U_DDR4_SODIMM|FileName=DDR4_SODIMM.schdoc|SheetNumber=3|SymbolType=Normal|RawFileName=DDR4_SODIMM.schdoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=DIOT_FMC_Carrier.SchDoc|Designator=U_FMC_Connector|SchDesignator=U_FMC_Connector|FileName=FMC_Connector.SchDoc|SheetNumber=2|SymbolType=Normal|RawFileName=FMC_Connector.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=DIOT_FMC_Carrier.SchDoc|Designator=U_FPGA_Bank_0_CFG|SchDesignator=U_FPGA_Bank_0_CFG|FileName=FPGA_Bank_0_CFG.SchDoc|SheetNumber=4|SymbolType=Normal|RawFileName=FPGA_Bank_0_CFG.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=DIOT_FMC_Carrier.SchDoc|Designator=U_FPGA_Bank_44-46_48_FMC|SchDesignator=U_FPGA_Bank_44-46_48_FMC|FileName=FPGA_Bank_44-46_48_FMC.SchDoc|SheetNumber=6|SymbolType=Normal|RawFileName=FPGA_Bank_44-46_48_FMC.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=DIOT_FMC_Carrier.SchDoc|Designator=U_FPGA_Bank_47_64_65|SchDesignator=U_FPGA_Bank_47_64_65|FileName=FPGA_Bank_47_64_65.SchDoc|SheetNumber=5|SymbolType=Normal|RawFileName=FPGA_Bank_47_64_65.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=DIOT_FMC_Carrier.SchDoc|Designator=U_FPGA_Bank_66_67_68_DDR|SchDesignator=U_FPGA_Bank_66_67_68_DDR|FileName=FPGA_Bank_66_67_68_DDR.SchDoc|SheetNumber=7|SymbolType=Normal|RawFileName=FPGA_Bank_66_67_68_DDR.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=DIOT_FMC_Carrier.SchDoc|Designator=U_FPGA_Bank_224-227_MGT|SchDesignator=U_FPGA_Bank_224-227_MGT|FileName=FPGA_Bank_224-227_MGT.SchDoc|SheetNumber=8|SymbolType=Normal|RawFileName=FPGA_Bank_224-227_MGT.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=DIOT_FMC_Carrier.SchDoc|Designator=U_FPGA_Supplies|SchDesignator=U_FPGA_Supplies|FileName=FPGA_Supplies.SchDoc|SheetNumber=9|SymbolType=Normal|RawFileName=FPGA_Supplies.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=DIOT_FMC_Carrier.SchDoc|Designator=U_Power_Supply_1|SchDesignator=U_Power_Supply_1|FileName=Power_Supply_1.SchDoc|SheetNumber=11|SymbolType=Normal|RawFileName=Power_Supply_1.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=DIOT_FMC_Carrier.SchDoc|Designator=U_Power_Supply_2|SchDesignator=U_Power_Supply_2|FileName=Power_Supply_2.SchDoc|SheetNumber=12|SymbolType=Normal|RawFileName=Power_Supply_2.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=DIOT_FMC_Carrier.SchDoc|Designator=U_Power_Supply_3|SchDesignator=U_Power_Supply_3|FileName=Power_Supply_3.SchDoc|SheetNumber=13|SymbolType=Normal|RawFileName=Power_Supply_3.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=DIOT_FMC_Carrier.SchDoc|Designator=U_Sensors|SchDesignator=U_Sensors|FileName=Sensors.SchDoc|SheetNumber=14|SymbolType=Normal|RawFileName=Sensors.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=DIOT_FMC_Carrier.SchDoc|Designator=U_USB_Quad|SchDesignator=U_USB_Quad|FileName=USB_Quad.SchDoc|SheetNumber=16|SymbolType=Normal|RawFileName=USB_Quad.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
hw/Simulation/DIOT_FMC_Carrier.bud
View file @ 40a04a07
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hw/Simulation/DIOT_FMC_Carrier.ddr 0 → 100644
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hw/Simulation/DIOT_FMC_Carrier.pjh
View file @ 40a04a07
[POWER_INTEGRITY]
CapAutoGrouping=0
AutoReferenceLayers=1
ConvertLargePadsToAreas_Convert=1
ConvertLargePadsToAreas_ApplyTo=0
AutoReferenceLayers=1
[EXPORT_TO_FFS]
EXPAND_INTO_EBD=1
EXPORT_VIA=0
......@@ -190,7 +190,7 @@ InclSelfCoupling=1
ArbitrayAngles=0
XtalkDataElectrical=0
CrosstalkVoltage=1.500000e-01
InclTraceToAreaCoupling=1
InclTraceToAreaCoupling=0
AreaConsiderDistance=1.016000e-03
AreaFillGrid=1.016000e-03
InclSparamCoupling=0
......
hw/Simulation/DIOT_PFC_DDR4.pjh 0 → 100644
View file @ 40a04a07
[VER]
Name=HyperLynx Project File
Major=1
Minor=1
[IAV]
TermWizTol=0
VICVi=1
IVCCi=1
XtF=0
XtE=0
XtV=1.500000e-01
XtGp=1.270000e-03
XtCl=1.270000e-02
IcSl=2.000000e-09
IcSVR=3.000000e+00
IcZ0=1.000000e+00
IcCi=7.000000e-12
EnableRigidFlex=0
SyncCommonStackupLayers=1
[VBP]
Thickness=3.175000e-05
CndFilled=0
Metal=Copper
Resistivity=1.724000e-08
[BATCH]
SiLRpt=
SiLCsv=
SiLXls=
SiLAudCsv=
QuickAll=1
SiDelay=1
SiSi=1
SiXtalk=0
ResultsFolder=Batch_Results
ResultsFolderTimeTag=1
SelNetMode=0
UseGlobalSimSettings=1
WasSavedInWizard=0
UseDefModel=0
DefModel_Library=modvsez.ibs
DefModel_Device=MODvsEZIBIS
DefModel_Pin=3
SelNets=
EMC=0
EmcFC=1
EmcCC=1
EmcVC=0
EmcUC=0
EmcCA=1
EmcCB=1
EmcMp=1
EmcPr=1
EmcTr=1
EmcAntD=3.000000e+00
EmcDvB=1
EmcDvT=0
EmcDvW=0
SI=0
SiDspRpt=1
SiHTMLrpt=1
SiDspCsv=0
SiSaveWave=0
SiShowWave=0
SiCsvFrm=0
SiRptLim=0
SiRt=9.000000e+02
SiMonot=1.000000e-04
SiDvB=1
SiDvT=1
SiDvW=1
SiDvBi=0
SiCpNb=0
XtDvLo=0
XtDvHi=0
XtQkS=1
XtThO=1
XtThr=1.500000e-01
XtAggr=1
XtAggrLim=15
SiFlTc=1
GViol=1
TViol=1
Lossy=1
SimVias=1
MGen=1
MStk=0
MCpI=1
MNtI=1
MCpN=0
TrcI=0
TrDl=1
TrmmZ=1
TrLn=1
TotC=1
TrC=1
PerTrC=1
TrL=1
PerTrL=1
TrR=1
PerTrR=1
TrZ=1
QTw=1
Tws=1
TwZ=1
TwIc=1
TwCd=1
IcSl=1.000000e-09
IcSVR=3.300000e+00
IcZ0=1.000000e+00
IcCi=7.000000e-12
VICVb=1
IVCCb=1
AudType=3
AudDC=0
AudOpen=1
[BATCH_SIM_SETTINGS]
TraceConsiderDistance=3.810000e-04
MinTotalCoupledTraceLength=1.270000e-02
TraceIgnoreShorterThan=2.540000e-03
ConsiderLayersLimit=1
ConsiderNetsNum=1
InclSelfCoupling=1
ArbitrayAngles=0
XtalkDataElectrical=0
CrosstalkVoltage=1.500000e-01
InclTraceToAreaCoupling=0
AreaConsiderDistance=1.016000e-03
AreaFillGrid=1.016000e-03
InclSparamCoupling=0
SparamMinFreq=1.000000e-01
SparamMaxFreq=2.000000e+04
InclPkgCoupling=1
PkgCouplingThreshold=-2.000000e+01
InclConnCoupling=1
ConnCouplingThreshold=-2.000000e+01
Incl3daCoupling=1
3daCouplingThreshold=-2.000000e+01
UseSameSparamCouplingThreshold=1
SameSparamCouplingThreshold=-2.000000e+01
ModelPowerPins=0
InclPowerBusCoupling=1
StartCycle=1
EndCycle=2
EdgeType=0
XtalkIterationsMode=0
MaxXtalkIterations=4
XtalkType=0
VictimLow=1
VictimHigh=1
VictimTri=1
UseXtalkInSI=0
PassiveAggInSI=0
AggSwitchType=0
SimTimeAuto=1
SimTime=1.000000e-08
MaxRoundRobinIterations=32
SimResAuto=1
SimResolution=1.000000e-11
[BATCH_DRIVERS]
NumberOfDrvCases=0
[PROBING]
Lsw=2
Bsw=0
[DEVICE_KIT]
INIFILE=
[ANTISETUP]
SHOWANTI=1
FORCEUSER=0
APAD=2.540000e-04
ASEG=2.032000e-04
[POWER_INTEGRITY]
ConvertLargePadsToAreas_Convert=1
ConvertLargePadsToAreas_ApplyTo=0
AutoReferenceLayers=1
[SI_SIM]
TraceConsiderDistance=3.810000e-04
MinTotalCoupledTraceLength=1.270000e-02
TraceIgnoreShorterThan=2.540000e-03
ConsiderLayersLimit=1
ConsiderNetsNum=1
InclSelfCoupling=1
ArbitrayAngles=0
XtalkDataElectrical=0
CrosstalkVoltage=1.500000e-01
InclTraceToAreaCoupling=0
AreaConsiderDistance=1.016000e-03
AreaFillGrid=1.016000e-03
InclSparamCoupling=0
SparamMinFreq=1.000000e-01
SparamMaxFreq=2.000000e+04
InclPkgCoupling=1
PkgCouplingThreshold=-2.000000e+01
InclConnCoupling=1
ConnCouplingThreshold=-2.000000e+01
Incl3daCoupling=1
3daCouplingThreshold=-2.000000e+01
UseSameSparamCouplingThreshold=1
SameSparamCouplingThreshold=-2.000000e+01
ModelPowerPins=0
InclPowerBusCoupling=1
StartCycle=1
EndCycle=2
EdgeType=0
XtalkIterationsMode=0
MaxXtalkIterations=4
XtalkType=0
VictimLow=1
VictimHigh=1
VictimTri=1
UseXtalkInSI=0
PassiveAggInSI=0
AggSwitchType=0
SimTimeAuto=1
SimTime=1.000000e-08
MaxRoundRobinIterations=32
SimResAuto=1
SimResolution=1.000000e-11
[Verify]
DelayAndSI=1
Xtalk=0
GlobalStimulus=1
OscLow=1
OscFreq=5.000000e+02
OscDuty=5.000000e+01
Corner=1
SaveWaveforms=1
OscSaveWfNrPoints=10
[3DAreaSearchOptions]
LayerSpanByConnectivity=1
AllowTwoLayerAreas=0
AllowSingleNets=1
StitchViaSearchDist=3.048000e-03
ReqObjClrance=2.540000e-04
CouplingDistance=2.540000e-04
MaxFreq=2.000000e+10
MatchPortMismatch=7.620000e-05
SigViaMismatch=7.620000e-05
StitchViaMismatch=7.620000e-05
StitchNumMismatch=0
DrillDiamMismatch=2.540000e-05
MatchGeom=1
SigAreaMismatch=1.000000e-01
SupplyAreaMismatch=1.500000e-01
[HlasOptions]
Folder=
[DIFF_PAIRS]
GenerateDiffPairs=0
[MSG_HANDLER]
Version=2
[PROJECT_SUB_FILES]
B00=.\DIOT_FMC_Carrier.tgz, ""
B01=D:\OneDrive\Praca\Creotech\DIOT_FMC_Carrier\diot-fmc-carrier\diot-fmc-carrier\hw\Simulation\Models\MTA9ASF1G72HZ-3G2R1_hyp\MTA9ASF1G72HZ-3G2R1.hyp, ""
[PROJECT_SUB_FILE_INTERCONNECT]
CONN0001=B00_SK1 B01_J1 R=0.001000 L=5.000000nH C=2.000000pF SHORT
[MSG_HANDLER_V2]
MessageBox00=Reg_CompletelyUnroutedPrompt,7
hw/Simulation/DIOT_PFC_DDR4.ref 0 → 100644
View file @ 40a04a07
*
* RefDef mapping from .\DIOT_FMC_Carrier.tgz
*
*
*BoardSim has generated this file for you from the Multi Board data
*
*
* RefDef mapping from D:\OneDrive\Praca\Creotech\DIOT_FMC_Carrier\diot-fmc-carrier\diot-fmc-carrier\hw\Simulation\Models\MTA9ASF1G72HZ-3G2R1_hyp\MTA9ASF1G72HZ-3G2R1.hyp
*
*
*BoardSim has generated this file for you from the Multi Board data
*
RN1_B01, 33.0ohms, , RES-DIP8-SERIES-1
RN3_B01, 33.0ohms, , RES-DIP8-SERIES-1
RN4_B01, 33.0ohms, , RES-DIP8-SERIES-1
RN5_B01, 33.0ohms, , RES-DIP8-SERIES-1
RN6_B01, 33.0ohms, , RES-DIP8-SERIES-1
RN7_B01, 33.0ohms, , RES-DIP8-SERIES-1
RN8_B01, 33.0ohms, , RES-DIP8-SERIES-1
RN2_B01, 30.0ohms, , RES-DIP4-SERIES-1
U10_B01, z41c.ibs, MT40A1G8SA
U8_B01, z41c.ibs, MT40A1G8SA
U7_B01, z41c.ibs, MT40A1G8SA
U6_B01, z41c.ibs, MT40A1G8SA
U5_B01, z41c.ibs, MT40A1G8SA
U4_B01, z41c.ibs, MT40A1G8SA
U3_B01, z41c.ibs, MT40A1G8SA
U2_B01, z41c.ibs, MT40A1G8SA
U9_B01, z41c.ibs, MT40A1G8SA
hw/Simulation/default.qpl 0 → 100644
View file @ 40a04a07
*
* Q[ualified] P[art] L[ist] file *
*
C, 1nF, "", 1.0nF
C, 1uF, "", 1.0uF
C, 2.2uF, "", 2.2uF
C, 4.7uF, "", 4.7uF
IC, XCKU035-1FFVA1156C, "", diot_pfc.ibs, kintexu
hw/sch/CPCIS_Connectors_P1_P4_P6.Harness
View file @ 40a04a07
BP_Conn=LVDS_P[0..14],LVDS_N[0..14],SHARED_BUS_[0..4],GA[0..3]
BP_RTM=IO[0..33],SHARED_BUS[0..7]
CLK_DIFF=CLK_P,CLK_N
I2C=SDA,SCL
JTAG5=TCK,TDI,TDO,TMS,TRSTn
MGT=Tx_P,Tx_N,Rx_P,Rx_N
BP_Conn=LVDS_P[0..14],LVDS_N[0..14],SHARED_BUS_[0..4],GA[0..3]
BP_RTM=IO[0..33],SHARED_BUS[0..7]
CLK_DIFF=CLK_P,CLK_N
I2C=SDA,SCL
JTAG5=TCK,TDI,TDO,TMS,TRSTn
MGT=Tx_P,Tx_N,Rx_P,Rx_N
hw/sch/Clocks.Harness
View file @ 40a04a07
CDR_PLL_CTRL=Main_DCXO_SDA,Main_DCXO_SCL,Main_DCXO_OE,Helper_DCXO_OE,Helper_DCXO_SDA,Helper_DCXO_SCL
CLK_DIFF=CLK_P,CLK_N
I2C=SDA,SCL
MGT_CLKREF_H=CLK_P[1..0],CLK_N[1..0]
CDR_PLL_CTRL=Main_DCXO_SDA,Main_DCXO_SCL,Main_DCXO_OE,Helper_DCXO_OE,Helper_DCXO_SDA,Helper_DCXO_SCL
CLK_DIFF=CLK_P,CLK_N
I2C=SDA,SCL
MGT_CLKREF_H=CLK_P[1..0],CLK_N[1..0]
hw/sch/DDR4_SODIMM.Harness
View file @ 40a04a07
DDR4_x64=CB[7..0],DQ[63..0],DM[8..0],DQS_P[8..0],DQS_N[8..0],A[16..0],CK_P[1..0],CK_N[1..0],CKE[1..0],RST_N,ACT_N,PAR,CS_N[3..0],ODT[1..0],BA[1..0],BG[1..0],ALERT_N,EVENT_n,{I2C:I2C}
I2C=SCL,SDA
DDR4_x64=CB[7..0],DQ[63..0],DM[8..0],DQS_P[8..0],DQS_N[8..0],A[16..0],CK_P[1..0],CK_N[1..0],CKE[1..0],RST_N,ACT_N,PAR,CS_N[3..0],ODT[1..0],BA[1..0],BG[1..0],ALERT_N,EVENT_n,{I2C:I2C}
I2C=SCL,SDA
hw/sch/FMC_Connector.Harness
View file @ 40a04a07
CLK_DIFF=CLK_P,CLK_N
FMC=LA_P[0..33],LA_N[0..33],HA_P[0..23],HA_N[0..23],HB_P[0..21],HB_N[0..21],VREFA_M2C,VREFB_M2C,CLK_DIR
FMC_CLK=CLK_M2C_P[0..1],CLK_M2C_N[0..1],CLK_BIDIR_P[2..3],CLK_BIDIR_N[2..3]
FMC_MGT=GBTCLK_M2C_P[0..1],GBTCLK_M2C_N[0..1],DP_C2M_P[0..9],DP_C2M_N[0..9],DP_M2C_P[0..9],DP_M2C_N[0..9]
I2C=SDA,SCL
JTAG5=TCK,TDI,TDO,TMS,TRSTn
CLK_DIFF=CLK_P,CLK_N
FMC=LA_P[0..33],LA_N[0..33],HA_P[0..23],HA_N[0..23],HB_P[0..21],HB_N[0..21],VREFA_M2C,VREFB_M2C,CLK_DIR
FMC_CLK=CLK_M2C_P[0..1],CLK_M2C_N[0..1],CLK_BIDIR_P[2..3],CLK_BIDIR_N[2..3]
FMC_MGT=GBTCLK_M2C_P[0..1],GBTCLK_M2C_N[0..1],DP_C2M_P[0..9],DP_C2M_N[0..9],DP_M2C_P[0..9],DP_M2C_N[0..9]
I2C=SDA,SCL
JTAG5=TCK,TDI,TDO,TMS,TRSTn
hw/sch/FPGA_Bank_0_CFG.Harness
View file @ 40a04a07
FPGA_THERM=DXP,DXN
JTAG5=TCK,TDI,TDO,TMS,TRSTn
FPGA_THERM=DXP,DXN
JTAG5=TCK,TDI,TDO,TMS,TRSTn
hw/sch/FPGA_Bank_224-227_MGT.Harness
View file @ 40a04a07
FMC_MGT=DP_C2M_N[0..9],DP_C2M_P[0..9],DP_M2C_N[0..9],DP_M2C_P[0..9],GBTCLK_M2C_N[0..1],GBTCLK_M2C_P[0..1]
MGT=Rx_P,Rx_N,Tx_P,Tx_N
MGT_CLKREF_H=CLK_P[1..0],CLK_N[1..0]
FMC_MGT=DP_C2M_N[0..9],DP_C2M_P[0..9],DP_M2C_N[0..9],DP_M2C_P[0..9],GBTCLK_M2C_N[0..1],GBTCLK_M2C_P[0..1]
MGT=Rx_P,Rx_N,Tx_P,Tx_N
MGT_CLKREF_H=CLK_P[1..0],CLK_N[1..0]
hw/sch/FPGA_Bank_44-46_48_FMC.Harness
View file @ 40a04a07
FMC=CLK_DIR,HA_N[0..23],HA_P[0..23],HB_N[0..21],HB_P[0..21],LA_N[0..33],LA_P[0..33],VREFA_M2C,VREFB_M2C
FMC_CLK=CLK_M2C_P[0..1],CLK_M2C_N[0..1],CLK_BIDIR_P[2..3],CLK_BIDIR_N[2..3]
FMC=CLK_DIR,HA_N[0..23],HA_P[0..23],HB_N[0..21],HB_P[0..21],LA_N[0..33],LA_P[0..33],VREFA_M2C,VREFB_M2C
FMC_CLK=CLK_M2C_P[0..1],CLK_M2C_N[0..1],CLK_BIDIR_P[2..3],CLK_BIDIR_N[2..3]
hw/sch/FPGA_Bank_47_64_65.Harness
View file @ 40a04a07
BP_Conn=GA[0..3],LVDS_P[0..14],LVDS_N[0..14],SHARED_BUS_[0..4]
BP_RTM=IO[0..33],SHARED_BUS[0..7]
CDR_PLL_CTRL=Helper_DCXO_OE,Helper_DCXO_SCL,Helper_DCXO_SDA,Main_DCXO_OE,Main_DCXO_SCL,Main_DCXO_SDA
CLK_DIFF=CLK_P,CLK_N
DDR4_x64={I2C:I2C},A[16..0],ACT_N,ALERT_N,BA[1..0],BG[1..0],CB[7..0],CK_N[1..0],CK_P[1..0],CKE[1..0],CS_N[3..0],DM[8..0],DQ[63..0],DQS_N[8..0],DQS_P[8..0],EVENT_n,ODT[1..0],PAR,RST_N
I2C=SCL,SDA
BP_Conn=GA[0..3],LVDS_P[0..14],LVDS_N[0..14],SHARED_BUS_[0..4]
BP_RTM=IO[0..33],SHARED_BUS[0..7]
CDR_PLL_CTRL=Helper_DCXO_OE,Helper_DCXO_SCL,Helper_DCXO_SDA,Main_DCXO_OE,Main_DCXO_SCL,Main_DCXO_SDA
CLK_DIFF=CLK_P,CLK_N
DDR4_x64={I2C:I2C},A[16..0],ACT_N,ALERT_N,BA[1..0],BG[1..0],CB[7..0],CK_N[1..0],CK_P[1..0],CKE[1..0],CS_N[3..0],DM[8..0],DQ[63..0],DQS_N[8..0],DQS_P[8..0],EVENT_n,ODT[1..0],PAR,RST_N
I2C=SCL,SDA
hw/sch/FPGA_Bank_66_67_68_DDR.Harness
View file @ 40a04a07
CLK_DIFF=CLK_P,CLK_N
DDR4_x64=CB[7..0],DQ[63..0],DM[8..0],DQS_P[8..0],DQS_N[8..0],A[16..0],CK_P[1..0],CK_N[1..0],CKE[1..0],RST_N,ACT_N,PAR,CS_N[3..0],ODT[1..0],BA[1..0],BG[1..0],ALERT_N,EVENT_n,{I2C:I2C}
CLK_DIFF=CLK_P,CLK_N
DDR4_x64=CB[7..0],DQ[63..0],DM[8..0],DQS_P[8..0],DQS_N[8..0],A[16..0],CK_P[1..0],CK_N[1..0],CKE[1..0],RST_N,ACT_N,PAR,CS_N[3..0],ODT[1..0],BA[1..0],BG[1..0],ALERT_N,EVENT_n,{I2C:I2C}
hw/sch/Sensors.Harness
View file @ 40a04a07
FPGA_THERM=DXP,DXN
I2C=SDA,SCL
FPGA_THERM=DXP,DXN
I2C=SDA,SCL
hw/sch/USB_Quad.Harness
View file @ 40a04a07
I2C=SDA,SCL
JTAG5=TDI,TCK,TMS,TDO,TRSTn
I2C=SDA,SCL
JTAG5=TDI,TCK,TMS,TDO,TRSTn
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