bootloader/atmel_start: make GCLK_GEN_0 and GCLK_GEN_3 run in standby

Clocks (even these not used) are changed to be very similar to main_fw Signed-off-by: Adam Wujek <dev_public@wujek.eu>

bootloader/atmel_start: make GCLK_GEN_0 and GCLK_GEN_3 run in standby
Clocks (even these not used) are changed to be very similar to main_fw Signed-off-by: Adam Wujek <dev_public@wujek.eu>
a2f6024a · Adam Wujek · 0e0d3b61 · a2f6024a · a2f6024a · a2f6024a
Commit a2f6024a authored May 16, 2022 by Adam Wujek
6 changed files
--- a/bootloader/atmel_start_prj/atmel_start_config.atstart
+++ b/bootloader/atmel_start_prj/atmel_start_config.atstart
@@ -26,18 +26,18 @@ drivers:
    functionality: System
    api: HAL:HPL:GCLK
    configuration:
-      $input: 48000000
+      $input: 8000000
-      $input_id: Digital Frequency Locked Loop (DFLL48M)
+      $input_id: External Crystal Oscillator 0.4-32MHz (XOSC)
-      RESERVED_InputFreq: 48000000
+      RESERVED_InputFreq: 8000000
-      RESERVED_InputFreq_id: Digital Frequency Locked Loop (DFLL48M)
+      RESERVED_InputFreq_id: External Crystal Oscillator 0.4-32MHz (XOSC)
      _$freq_output_Generic clock generator 0: 24000000
      _$freq_output_Generic clock generator 1: 31250
      _$freq_output_Generic clock generator 2: 48000000
      _$freq_output_Generic clock generator 3: 400000
      _$freq_output_Generic clock generator 4: 8000000
-      _$freq_output_Generic clock generator 5: 400000
+      _$freq_output_Generic clock generator 5: 8000000
-      _$freq_output_Generic clock generator 6: 400000
+      _$freq_output_Generic clock generator 6: 8000000
-      _$freq_output_Generic clock generator 7: 400000
+      _$freq_output_Generic clock generator 7: 8000000
      enable_gclk_gen_0: true
      enable_gclk_gen_0__externalclock: 1000000
      enable_gclk_gen_1: true
@@ -54,7 +54,7 @@ drivers:
      enable_gclk_gen_6__externalclock: 1000000
      enable_gclk_gen_7: false
      enable_gclk_gen_7__externalclock: 1000000
-      gclk_arch_gen_0_RUNSTDBY: false
+      gclk_arch_gen_0_RUNSTDBY: true
      gclk_arch_gen_0_enable: true
      gclk_arch_gen_0_idc: false
      gclk_arch_gen_0_oe: false
@@ -64,12 +64,12 @@ drivers:
      gclk_arch_gen_1_idc: false
      gclk_arch_gen_1_oe: false
      gclk_arch_gen_1_oov: false
-      gclk_arch_gen_2_RUNSTDBY: false
+      gclk_arch_gen_2_RUNSTDBY: true
-      gclk_arch_gen_2_enable: false
+      gclk_arch_gen_2_enable: true
      gclk_arch_gen_2_idc: false
      gclk_arch_gen_2_oe: false
      gclk_arch_gen_2_oov: false
-      gclk_arch_gen_3_RUNSTDBY: false
+      gclk_arch_gen_3_RUNSTDBY: true
      gclk_arch_gen_3_enable: true
      gclk_arch_gen_3_idc: false
      gclk_arch_gen_3_oe: false
@@ -97,7 +97,7 @@ drivers:
      gclk_gen_0_div: 2
      gclk_gen_0_div_sel: false
      gclk_gen_0_oscillator: Digital Frequency Locked Loop (DFLL48M)
-      gclk_gen_1_div: 32
+      gclk_gen_1_div: 256
      gclk_gen_1_div_sel: false
      gclk_gen_1_oscillator: 8MHz Internal Oscillator (OSC8M)
      gclk_gen_2_div: 1
@@ -139,7 +139,7 @@ drivers:
      cpu_clock_source: Generic clock generator 0
      cpu_div: '1'
      enable_cpu_clock: true
-      nvm_wait_states: '1'
+      nvm_wait_states: '0'
    optional_signals: []
    variant: null
    clocks:
@@ -162,7 +162,7 @@ drivers:
      i2c_slave_amode: Mask
      i2c_slave_gencen: false
      i2c_slave_lowtout: false
-      i2c_slave_runstdby: false
+      i2c_slave_runstdby: true
      i2c_slave_sclsm: false
      i2c_slave_sdahold: 300-600ns hold time
      i2c_slave_sexttoen: false
@@ -477,14 +477,14 @@ drivers:
    functionality: System
    api: HAL:HPL:SYSCTRL
    configuration:
-      $input: 31250
+      $input: 31007.751937984496
-      $input_id: Generic clock generator 1
+      $input_id: External Crystal Oscillator 0.4-32MHz (XOSC)
-      RESERVED_InputFreq: 31250
+      RESERVED_InputFreq: 31007.751937984496
-      RESERVED_InputFreq_id: Generic clock generator 1
+      RESERVED_InputFreq_id: External Crystal Oscillator 0.4-32MHz (XOSC)
-      _$freq_output_8MHz Internal Oscillator (OSC8M): 1000000
+      _$freq_output_8MHz Internal Oscillator (OSC8M): 8000000
      _$freq_output_Digital Frequency Locked Loop (DFLL48M): 48000000
-      _$freq_output_External Crystal Oscillator 0.4-32MHz (XOSC): 400000
+      _$freq_output_External Crystal Oscillator 0.4-32MHz (XOSC): '8000000'
-      _$freq_output_Fractional Digital Phase Locked Loop (FDPLL96M): 45775390.625
+      _$freq_output_Fractional Digital Phase Locked Loop (FDPLL96M): 186046.511627907
      dfll48m_arch_bplckc: false
      dfll48m_arch_calibration: false
      dfll48m_arch_ccdis: true
@@ -494,12 +494,12 @@ drivers:
      dfll48m_arch_llaw: false
      dfll48m_arch_ondemand: false
      dfll48m_arch_qldis: false
-      dfll48m_arch_runstdby: false
+      dfll48m_arch_runstdby: true
      dfll48m_arch_stable: false
-      dfll48m_arch_usbcrm: true
+      dfll48m_arch_usbcrm: false
      dfll48m_arch_waitlock: false
      dfll48m_mode: Closed Loop Mode
-      dfll48m_mul: 48000
+      dfll48m_mul: 1536
      dfll48m_ref_clock: Generic clock generator 1
      dfll_arch_cstep: 3
      dfll_arch_fstep: 31
@@ -514,10 +514,10 @@ drivers:
      fdpll96m_arch_lbypass: true
      fdpll96m_arch_ondemand: false
      fdpll96m_arch_runstdby: false
-      fdpll96m_clock_div: 1
+      fdpll96m_clock_div: 128
-      fdpll96m_ldr: 1463
+      fdpll96m_ldr: 5
-      fdpll96m_ldrfrac: 13
+      fdpll96m_ldrfrac: 0
-      fdpll96m_ref_clock: Generic clock generator 1
+      fdpll96m_ref_clock: External Crystal Oscillator 0.4-32MHz (XOSC)
      osc32k_arch_calib: 0
      osc32k_arch_en1k: false
      osc32k_arch_en32k: false
@@ -531,8 +531,8 @@ drivers:
      osc8m_arch_enable: true
      osc8m_arch_ondemand: true
      osc8m_arch_overwrite_calibration: false
-      osc8m_arch_runstdby: false
+      osc8m_arch_runstdby: true
-      osc8m_presc: '8'
+      osc8m_presc: '1'
      osculp32k_arch_calib: 0
      osculp32k_arch_overwrite_calibration: false
      osculp32k_arch_wrtlock: false
@@ -545,14 +545,14 @@ drivers:
      xosc32k_arch_startup: 122 us
      xosc32k_arch_wrtlock: false
      xosc32k_arch_xtalen: true
-      xosc_arch_ampgc: false
+      xosc_arch_ampgc: true
      xosc_arch_enable: false
-      xosc_arch_gain: 2Mhz
+      xosc_arch_gain: 8Mhz
-      xosc_arch_ondemand: true
+      xosc_arch_ondemand: false
-      xosc_arch_runstdby: false
+      xosc_arch_runstdby: true
-      xosc_arch_startup: 31 us
+      xosc_arch_startup: 125000 us
-      xosc_arch_xtalen: false
+      xosc_arch_xtalen: true
-      xosc_frequency: 400000
+      xosc_frequency: 8000000
    optional_signals: []
    variant: null
    clocks:

--- a/bootloader/atmel_start_prj/config/hpl_gclk_config.h
+++ b/bootloader/atmel_start_prj/config/hpl_gclk_config.h
@@ -16,7 +16,7 @@
 // <i> Indicates whether Run in Standby is enabled or not
 // <id> gclk_arch_gen_0_RUNSTDBY
 #ifndef CONF_GCLK_GEN_0_RUNSTDBY
-#define CONF_GCLK_GEN_0_RUNSTDBY 0
+#define CONF_GCLK_GEN_0_RUNSTDBY 1
 #endif
 // <q> Divide Selection
@@ -151,7 +151,7 @@
 // <i>
 // <id> gclk_gen_1_div
 #ifndef CONF_GCLK_GEN_1_DIV
-#define CONF_GCLK_GEN_1_DIV 32
+#define CONF_GCLK_GEN_1_DIV 256
 #endif
 // </h>
@@ -167,7 +167,7 @@
 // <i> Indicates whether Run in Standby is enabled or not
 // <id> gclk_arch_gen_2_RUNSTDBY
 #ifndef CONF_GCLK_GEN_2_RUNSTDBY
-#define CONF_GCLK_GEN_2_RUNSTDBY 0
+#define CONF_GCLK_GEN_2_RUNSTDBY 1
 #endif
 // <q> Divide Selection
@@ -202,7 +202,7 @@
 // <i> Indicates whether Generic Clock Generator Enable is enabled or not
 // <id> gclk_arch_gen_2_enable
 #ifndef CONF_GCLK_GEN_2_GENEN
-#define CONF_GCLK_GEN_2_GENEN 0
+#define CONF_GCLK_GEN_2_GENEN 1
 #endif
 // <y> Generic clock generator 2 source
@@ -243,7 +243,7 @@
 // <i> Indicates whether Run in Standby is enabled or not
 // <id> gclk_arch_gen_3_RUNSTDBY
 #ifndef CONF_GCLK_GEN_3_RUNSTDBY
-#define CONF_GCLK_GEN_3_RUNSTDBY 0
+#define CONF_GCLK_GEN_3_RUNSTDBY 1
 #endif
 // <q> Divide Selection

--- a/bootloader/atmel_start_prj/config/hpl_pm_config.h
+++ b/bootloader/atmel_start_prj/config/hpl_pm_config.h
@@ -59,7 +59,7 @@
 // <15=> 15
 // <id> nvm_wait_states
 #ifndef CONF_NVM_WAIT_STATE
-#define CONF_NVM_WAIT_STATE 1
+#define CONF_NVM_WAIT_STATE 0
 #endif
 // </h>

--- a/bootloader/atmel_start_prj/config/hpl_sercom_config.h
+++ b/bootloader/atmel_start_prj/config/hpl_sercom_config.h
@@ -35,7 +35,7 @@
 // <i> Determine if the module shall run in standby sleep mode
 // <id> i2c_slave_runstdby
 #ifndef CONF_SERCOM_2_I2CS_RUNSTDBY
-#define CONF_SERCOM_2_I2CS_RUNSTDBY 0
+#define CONF_SERCOM_2_I2CS_RUNSTDBY 1
 #endif
 // <o> SDA Hold Time (SDAHOLD)

--- a/bootloader/atmel_start_prj/config/hpl_sysctrl_config.h
+++ b/bootloader/atmel_start_prj/config/hpl_sysctrl_config.h
@@ -72,7 +72,7 @@
 // <i> If this bit is 1: The oscillator is not stopped in standby sleep mode.
 // <id> osc8m_arch_runstdby
 #ifndef CONF_OSC8M_RUNSTDBY
-#define CONF_OSC8M_RUNSTDBY 0
+#define CONF_OSC8M_RUNSTDBY 1
 #endif
 // <y> Prescaler
@@ -84,7 +84,7 @@
 // <i> Default: No Prescaling
 // <id> osc8m_presc
 #ifndef CONF_OSC8M_PRESC
-#define CONF_OSC8M_PRESC SYSCTRL_OSC8M_PRESC_3_Val
+#define CONF_OSC8M_PRESC SYSCTRL_OSC8M_PRESC_0_Val
 #endif
 // <q> Overwrite Default Osc Calibration
@@ -291,7 +291,7 @@
 // <i> Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator.
 // <id> xosc_frequency
 #ifndef CONF_XOSC_FREQUENCY
-#define CONF_XOSC_FREQUENCY 400000
+#define CONF_XOSC_FREQUENCY 8000000
 #endif
 // <h> External Multipurpose Crystal Oscillator (XOSC) Control
@@ -308,7 +308,7 @@
 // <i> If this bit is 1: the oscillator will only be running when requested by a peripheral.
 // <id> xosc_arch_ondemand
 #ifndef CONF_XOSC_ONDEMAND
-#define CONF_XOSC_ONDEMAND 1
+#define CONF_XOSC_ONDEMAND 0
 #endif
 // <q> Run In Standby
@@ -317,21 +317,21 @@
 // <i> If this bit is 1: The oscillator is not stopped in standby sleep mode.
 // <id> xosc_arch_runstdby
 #ifndef CONF_XOSC_RUNSTDBY
-#define CONF_XOSC_RUNSTDBY 0
+#define CONF_XOSC_RUNSTDBY 1
 #endif
 // <q> Enable XTAL
 // <i> Enable XTAL
 // <id> xosc_arch_xtalen
 #ifndef CONF_XOSC_XTALEN
-#define CONF_XOSC_XTALEN 0
+#define CONF_XOSC_XTALEN 1
 #endif
 // <q> Automatic Amplitude Control Enable
 // <i> Indicates whether Automatic Amplitude Control is Enabled or not
 // <id> xosc_arch_ampgc
 #ifndef CONF_XOSC_AMPGC
-#define CONF_XOSC_AMPGC 0
+#define CONF_XOSC_AMPGC 1
 #endif
 // <y> Gain of the Oscillator
@@ -343,7 +343,7 @@
 // <i> Select the Gain of the oscillator
 // <id> xosc_arch_gain
 #ifndef CONF_XOSC_GAIN
-#define CONF_XOSC_GAIN SYSCTRL_XOSC_GAIN_0_Val
+#define CONF_XOSC_GAIN SYSCTRL_XOSC_GAIN_2_Val
 #endif
 // <y> Start up time for the External Oscillator
@@ -367,7 +367,7 @@
 // <i> Default: 31 us
 // <id> xosc_arch_startup
 #ifndef CONF_XOSC_STARTUP
-#define CONF_XOSC_STARTUP CONF_XOSC_STARTUP_TIME_31MCS
+#define CONF_XOSC_STARTUP CONF_XOSC_STARTUP_TIME_125000MCS
 #endif
 // </h>
@@ -479,14 +479,14 @@
 // <i> If this bit is 1: The DFLL is not stopped in standby sleep mode.
 // <id> dfll48m_arch_runstdby
 #ifndef CONF_DFLL_RUNSTDBY
-#define CONF_DFLL_RUNSTDBY 0
+#define CONF_DFLL_RUNSTDBY 1
 #endif
 // <q> USB Clock Recovery Mode
 // <i> USB Clock Recovery Mode
 // <id> dfll48m_arch_usbcrm
 #ifndef CONF_DFLL_USBCRM
-#define CONF_DFLL_USBCRM 1
+#define CONF_DFLL_USBCRM 0
 #endif
 #if CONF_DFLL_USBCRM == 1
@@ -540,7 +540,7 @@
 //  <i> Default: 0
 //  <id> dfll48m_mul
 #ifndef CONF_DFLL_MUL
-#define CONF_DFLL_MUL 48000
+#define CONF_DFLL_MUL 1536
 #endif
 // <e> DFLL Calibration Overwrite
@@ -600,7 +600,7 @@
 // <i> Select the clock source.
 // <id> fdpll96m_ref_clock
 #ifndef CONF_DPLL_GCLK
-#define CONF_DPLL_GCLK GCLK_CLKCTRL_GEN_GCLK1_Val
+#define CONF_DPLL_GCLK GCLK_GENCTRL_SRC_XOSC
 #endif
 #if (CONF_DPLL_GCLK == GCLK_GENCTRL_SRC_XOSC32K)
@@ -648,21 +648,21 @@
 // <i> Clock Division Factor (Applicable if reference clock is XOSC)
 // <id> fdpll96m_clock_div
 #ifndef CONF_DPLL_DIV
-#define CONF_DPLL_DIV 1
+#define CONF_DPLL_DIV 128
 #endif
 // <o>DPLL LDRFRAC<0-15>
 // <i> Set the  fractional part of the frequency multiplier.
 // <id> fdpll96m_ldrfrac
 #ifndef CONF_DPLL_LDRFRAC
-#define CONF_DPLL_LDRFRAC 13
+#define CONF_DPLL_LDRFRAC 0
 #endif
 // <o>DPLL LDR <0-4095>
 // <i> Set the  integer part of the frequency multiplier.
 // <id> fdpll96m_ldr
 #ifndef CONF_DPLL_LDR
-#define CONF_DPLL_LDR 1463
+#define CONF_DPLL_LDR 5
 #endif
 // </h>

--- a/bootloader/atmel_start_prj/hpl/core/hpl_init.c
+++ b/bootloader/atmel_start_prj/hpl/core/hpl_init.c
@@ -41,10 +41,11 @@
 #include <hpl_dmac_config.h>
 /* Referenced GCLKs (out of 0~7), should be initialized firstly
+ * - GCLK 1 for DFLL48M
 */
-#define _GCLK_INIT_1ST 0x00000000
+#define _GCLK_INIT_1ST 0x00000002
 /* Not referenced GCLKs, initialized last */
-#define _GCLK_INIT_LAST 0x000000FF
+#define _GCLK_INIT_LAST 0x000000FD
 /**
 * \brief Initialize the hardware abstraction layer