bootloader/atmel_start: use 8MHz for i2c

Clock is chaned to 8MHz for i2c to be the same as in main_fw Signed-off-by: Adam Wujek <dev_public@wujek.eu>

bootloader/atmel_start: use 8MHz for i2c
Clock is chaned to 8MHz for i2c to be the same as in main_fw Signed-off-by: Adam Wujek <dev_public@wujek.eu>
0e0d3b61 · Adam Wujek · cf1de06a · 0e0d3b61 · 0e0d3b61 · 0e0d3b61
Commit 0e0d3b61 authored May 16, 2022 by Adam Wujek
3 changed files
--- a/bootloader/atmel_start_prj/atmel_start_config.atstart
+++ b/bootloader/atmel_start_prj/atmel_start_config.atstart
@@ -26,15 +26,15 @@ drivers:
    functionality: System
    api: HAL:HPL:GCLK
    configuration:
-      $input: 400000
-      $input_id: External Crystal Oscillator 0.4-32MHz (XOSC)
-      RESERVED_InputFreq: 400000
-      RESERVED_InputFreq_id: External Crystal Oscillator 0.4-32MHz (XOSC)
+      $input: 48000000
+      $input_id: Digital Frequency Locked Loop (DFLL48M)
+      RESERVED_InputFreq: 48000000
+      RESERVED_InputFreq_id: Digital Frequency Locked Loop (DFLL48M)
      _$freq_output_Generic clock generator 0: 24000000
      _$freq_output_Generic clock generator 1: 31250
      _$freq_output_Generic clock generator 2: 48000000
      _$freq_output_Generic clock generator 3: 400000
-      _$freq_output_Generic clock generator 4: 400000
+      _$freq_output_Generic clock generator 4: 8000000
      _$freq_output_Generic clock generator 5: 400000
      _$freq_output_Generic clock generator 6: 400000
      _$freq_output_Generic clock generator 7: 400000
@@ -46,7 +46,7 @@ drivers:
      enable_gclk_gen_2__externalclock: 1000000
      enable_gclk_gen_3: true
      enable_gclk_gen_3__externalclock: 1000000
-      enable_gclk_gen_4: false
+      enable_gclk_gen_4: true
      enable_gclk_gen_4__externalclock: 1000000
      enable_gclk_gen_5: false
      enable_gclk_gen_5__externalclock: 1000000
@@ -75,7 +75,7 @@ drivers:
      gclk_arch_gen_3_oe: false
      gclk_arch_gen_3_oov: false
      gclk_arch_gen_4_RUNSTDBY: false
-      gclk_arch_gen_4_enable: false
+      gclk_arch_gen_4_enable: true
      gclk_arch_gen_4_idc: false
      gclk_arch_gen_4_oe: false
      gclk_arch_gen_4_oov: false
@@ -106,9 +106,9 @@ drivers:
      gclk_gen_3_div: 120
      gclk_gen_3_div_sel: false
      gclk_gen_3_oscillator: Digital Frequency Locked Loop (DFLL48M)
-      gclk_gen_4_div: 1
+      gclk_gen_4_div: 6
      gclk_gen_4_div_sel: false
-      gclk_gen_4_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC)
+      gclk_gen_4_oscillator: Digital Frequency Locked Loop (DFLL48M)
      gclk_gen_5_div: 1
      gclk_gen_5_div_sel: false
      gclk_gen_5_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC)
@@ -181,7 +181,7 @@ drivers:
      domain_group:
        nodes:
        - name: Core
-          input: Generic clock generator 0
+          input: Generic clock generator 4
          external: false
          external_frequency: 0
        - name: Slow
@@ -189,7 +189,7 @@ drivers:
          external: false
          external_frequency: 0
        configuration:
-          core_gclk_selection: Generic clock generator 0
+          core_gclk_selection: Generic clock generator 4
          slow_gclk_selection: Generic clock generator 3
  DMAC:
    user_label: DMAC

--- a/bootloader/atmel_start_prj/config/hpl_gclk_config.h
+++ b/bootloader/atmel_start_prj/config/hpl_gclk_config.h
@@ -311,7 +311,7 @@
 // <i> Indicates whether generic clock 4 configuration is enabled or not
 // <id> enable_gclk_gen_4
 #ifndef CONF_GCLK_GENERATOR_4_CONFIG
-#define CONF_GCLK_GENERATOR_4_CONFIG 0
+#define CONF_GCLK_GENERATOR_4_CONFIG 1
 #endif

 // <h> Generic Clock Generator Control
@@ -354,7 +354,7 @@
 // <i> Indicates whether Generic Clock Generator Enable is enabled or not
 // <id> gclk_arch_gen_4_enable
 #ifndef CONF_GCLK_GEN_4_GENEN
-#define CONF_GCLK_GEN_4_GENEN 0
+#define CONF_GCLK_GEN_4_GENEN 1
 #endif

 // <y> Generic clock generator 4 source
@@ -370,7 +370,7 @@
 // <i> This defines the clock source for generic clock generator 4
 // <id> gclk_gen_4_oscillator
 #ifndef CONF_GCLK_GEN_4_SRC
-#define CONF_GCLK_GEN_4_SRC GCLK_GENCTRL_SRC_XOSC
+#define CONF_GCLK_GEN_4_SRC GCLK_GENCTRL_SRC_DFLL48M
 #endif
 // </h>

@@ -379,7 +379,7 @@
 // <i>
 // <id> gclk_gen_4_div
 #ifndef CONF_GCLK_GEN_4_DIV
-#define CONF_GCLK_GEN_4_DIV 1
+#define CONF_GCLK_GEN_4_DIV 6
 #endif

 // </h>

--- a/bootloader/atmel_start_prj/config/peripheral_clk_config.h
+++ b/bootloader/atmel_start_prj/config/peripheral_clk_config.h
@@ -33,7 +33,7 @@

 // <i> Select the clock source for CORE.
 #ifndef CONF_GCLK_SERCOM2_CORE_SRC
-#define CONF_GCLK_SERCOM2_CORE_SRC GCLK_CLKCTRL_GEN_GCLK0_Val
+#define CONF_GCLK_SERCOM2_CORE_SRC GCLK_CLKCTRL_GEN_GCLK4_Val
 #endif

 // <y> Slow Clock Source
@@ -65,7 +65,7 @@
 * \brief SERCOM2's Core Clock frequency
 */
 #ifndef CONF_GCLK_SERCOM2_CORE_FREQUENCY
-#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 24000000
+#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 8000000
 #endif

 /**