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DIOT Monitoring Module
DIOT Monitoring Module
Commit 165bfb65 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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Merge branch 'Adam WP1'

parents e1b97a8f b414abec
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    .gitlab-ci.yml
    View file @ 165bfb65
    stages:
    - make_main_fw
    - build_fw
    make_main_fw:
    stage: make_main_fw
    stage: build_fw
    tags:
    - arm-clang-coast
    script:
    ......@@ -12,3 +12,27 @@ make_main_fw:
    paths:
    - main_fw/build/main_fw.lss
    - main_fw/build/main_fw.bin
    make_bootloader_fw:
    stage: build_fw
    tags:
    - arm-clang-coast
    script:
    - cd bootloader/build && make -j5 all
    artifacts:
    name: BOOTLOADER_FW_CI_$CI_JOB_ID
    paths:
    - bootloader/build/bootloader.lss
    - bootloader/build/bootloader.bin
    make_test_master_fw:
    stage: build_fw
    tags:
    - arm-clang-coast
    script:
    - cd test_master/build && make -j5 all
    artifacts:
    name: TEST_MASTER_FW_CI_$CI_JOB_ID
    paths:
    - test_master/build/test_master.lss
    - test_master/build/test_master.bin
    bootloader/atmel_start_prj/armcc/Makefile
    View file @ 165bfb65
    ......@@ -27,16 +27,16 @@ endif
    # List the subdirectories for creating object files
    SUB_DIRS += \
    \
    samd21a/armcc/Device/SAMD21A/Source \
    hpl/dmac \
    samd21a/armcc/Device/SAMD21/Source \
    hal/src \
    hpl/pm \
    samd21a/armcc/Device/SAMD21/Source/ARM \
    hpl/sysctrl \
    hal/utils/src \
    hpl/sercom \
    examples \
    hpl/gclk \
    samd21a/armcc/Device/SAMD21A/Source/ARM \
    hpl/core
    # List the object files
    ......@@ -44,6 +44,7 @@ OBJS += \
    hal/src/hal_io.o \
    hal/src/hal_i2c_s_async.o \
    hal/src/hal_delay.o \
    samd21a/armcc/Device/SAMD21A/Source/system_samd21.o \
    hpl/pm/hpl_pm.o \
    hpl/core/hpl_init.o \
    hal/utils/src/utils_list.o \
    ......@@ -53,11 +54,10 @@ hpl/dmac/hpl_dmac.o \
    hpl/sysctrl/hpl_sysctrl.o \
    hpl/gclk/hpl_gclk.o \
    hal/src/hal_init.o \
    samd21a/armcc/Device/SAMD21/Source/ARM/startup_SAMD21.o \
    main.o \
    examples/driver_examples.o \
    driver_init.o \
    samd21a/armcc/Device/SAMD21/Source/system_samd21.o \
    samd21a/armcc/Device/SAMD21A/Source/ARM/startup_SAMD21.o \
    hpl/sercom/hpl_sercom.o \
    hal/utils/src/utils_ringbuffer.o \
    hal/src/hal_gpio.o \
    ......@@ -70,6 +70,7 @@ OBJS_AS_ARGS += \
    "hal/src/hal_io.o" \
    "hal/src/hal_i2c_s_async.o" \
    "hal/src/hal_delay.o" \
    "samd21a/armcc/Device/SAMD21A/Source/system_samd21.o" \
    "hpl/pm/hpl_pm.o" \
    "hpl/core/hpl_init.o" \
    "hal/utils/src/utils_list.o" \
    ......@@ -79,11 +80,10 @@ OBJS_AS_ARGS += \
    "hpl/sysctrl/hpl_sysctrl.o" \
    "hpl/gclk/hpl_gclk.o" \
    "hal/src/hal_init.o" \
    "samd21a/armcc/Device/SAMD21/Source/ARM/startup_SAMD21.o" \
    "main.o" \
    "examples/driver_examples.o" \
    "driver_init.o" \
    "samd21a/armcc/Device/SAMD21/Source/system_samd21.o" \
    "samd21a/armcc/Device/SAMD21A/Source/ARM/startup_SAMD21.o" \
    "hpl/sercom/hpl_sercom.o" \
    "hal/utils/src/utils_ringbuffer.o" \
    "hal/src/hal_gpio.o" \
    ......@@ -99,16 +99,15 @@ DEPS_AS_ARGS += \
    "hal/src/hal_gpio.d" \
    "hal/src/hal_io.d" \
    "hal/src/hal_i2c_s_async.d" \
    "samd21a/armcc/Device/SAMD21/Source/system_samd21.d" \
    "hpl/core/hpl_core_m0plus_base.d" \
    "hal/utils/src/utils_list.d" \
    "hpl/dmac/hpl_dmac.d" \
    "hal/utils/src/utils_assert.d" \
    "samd21a/armcc/Device/SAMD21A/Source/system_samd21.d" \
    "hal/src/hal_delay.d" \
    "hpl/core/hpl_init.d" \
    "hpl/sysctrl/hpl_sysctrl.d" \
    "hpl/gclk/hpl_gclk.d" \
    "samd21a/armcc/Device/SAMD21/Source/ARM/startup_SAMD21.d" \
    "hal/src/hal_init.d" \
    "driver_init.d" \
    "main.d" \
    ......@@ -116,6 +115,7 @@ DEPS_AS_ARGS += \
    "hal/src/hal_sleep.d" \
    "hal/utils/src/utils_ringbuffer.d" \
    "hpl/sercom/hpl_sercom.d" \
    "samd21a/armcc/Device/SAMD21A/Source/ARM/startup_SAMD21.d" \
    "hal/utils/src/utils_event.d" \
    "hal/src/hal_atomic.d" \
    "hpl/pm/hpl_pm.d" \
    ......
    bootloader/atmel_start_prj/atmel_start_config.atstart
    View file @ 165bfb65
    ......@@ -26,18 +26,18 @@ drivers:
    functionality: System
    api: HAL:HPL:GCLK
    configuration:
    $input: 48000000
    $input_id: Digital Frequency Locked Loop (DFLL48M)
    RESERVED_InputFreq: 48000000
    RESERVED_InputFreq_id: Digital Frequency Locked Loop (DFLL48M)
    $input: 8000000
    $input_id: External Crystal Oscillator 0.4-32MHz (XOSC)
    RESERVED_InputFreq: 8000000
    RESERVED_InputFreq_id: External Crystal Oscillator 0.4-32MHz (XOSC)
    _$freq_output_Generic clock generator 0: 24000000
    _$freq_output_Generic clock generator 1: 31250
    _$freq_output_Generic clock generator 2: 48000000
    _$freq_output_Generic clock generator 3: 400000
    _$freq_output_Generic clock generator 4: 400000
    _$freq_output_Generic clock generator 5: 400000
    _$freq_output_Generic clock generator 6: 400000
    _$freq_output_Generic clock generator 7: 400000
    _$freq_output_Generic clock generator 4: 8000000
    _$freq_output_Generic clock generator 5: 8000000
    _$freq_output_Generic clock generator 6: 8000000
    _$freq_output_Generic clock generator 7: 8000000
    enable_gclk_gen_0: true
    enable_gclk_gen_0__externalclock: 1000000
    enable_gclk_gen_1: true
    ......@@ -46,7 +46,7 @@ drivers:
    enable_gclk_gen_2__externalclock: 1000000
    enable_gclk_gen_3: true
    enable_gclk_gen_3__externalclock: 1000000
    enable_gclk_gen_4: false
    enable_gclk_gen_4: true
    enable_gclk_gen_4__externalclock: 1000000
    enable_gclk_gen_5: false
    enable_gclk_gen_5__externalclock: 1000000
    ......@@ -54,7 +54,7 @@ drivers:
    enable_gclk_gen_6__externalclock: 1000000
    enable_gclk_gen_7: false
    enable_gclk_gen_7__externalclock: 1000000
    gclk_arch_gen_0_RUNSTDBY: false
    gclk_arch_gen_0_RUNSTDBY: true
    gclk_arch_gen_0_enable: true
    gclk_arch_gen_0_idc: false
    gclk_arch_gen_0_oe: false
    ......@@ -64,18 +64,18 @@ drivers:
    gclk_arch_gen_1_idc: false
    gclk_arch_gen_1_oe: false
    gclk_arch_gen_1_oov: false
    gclk_arch_gen_2_RUNSTDBY: false
    gclk_arch_gen_2_enable: false
    gclk_arch_gen_2_RUNSTDBY: true
    gclk_arch_gen_2_enable: true
    gclk_arch_gen_2_idc: false
    gclk_arch_gen_2_oe: false
    gclk_arch_gen_2_oov: false
    gclk_arch_gen_3_RUNSTDBY: false
    gclk_arch_gen_3_RUNSTDBY: true
    gclk_arch_gen_3_enable: true
    gclk_arch_gen_3_idc: false
    gclk_arch_gen_3_oe: false
    gclk_arch_gen_3_oov: false
    gclk_arch_gen_4_RUNSTDBY: false
    gclk_arch_gen_4_enable: false
    gclk_arch_gen_4_RUNSTDBY: true
    gclk_arch_gen_4_enable: true
    gclk_arch_gen_4_idc: false
    gclk_arch_gen_4_oe: false
    gclk_arch_gen_4_oov: false
    ......@@ -97,7 +97,7 @@ drivers:
    gclk_gen_0_div: 2
    gclk_gen_0_div_sel: false
    gclk_gen_0_oscillator: Digital Frequency Locked Loop (DFLL48M)
    gclk_gen_1_div: 32
    gclk_gen_1_div: 256
    gclk_gen_1_div_sel: false
    gclk_gen_1_oscillator: 8MHz Internal Oscillator (OSC8M)
    gclk_gen_2_div: 1
    ......@@ -106,9 +106,9 @@ drivers:
    gclk_gen_3_div: 120
    gclk_gen_3_div_sel: false
    gclk_gen_3_oscillator: Digital Frequency Locked Loop (DFLL48M)
    gclk_gen_4_div: 1
    gclk_gen_4_div: 6
    gclk_gen_4_div_sel: false
    gclk_gen_4_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC)
    gclk_gen_4_oscillator: Digital Frequency Locked Loop (DFLL48M)
    gclk_gen_5_div: 1
    gclk_gen_5_div_sel: false
    gclk_gen_5_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC)
    ......@@ -139,7 +139,7 @@ drivers:
    cpu_clock_source: Generic clock generator 0
    cpu_div: '1'
    enable_cpu_clock: true
    nvm_wait_states: '1'
    nvm_wait_states: '0'
    optional_signals: []
    variant: null
    clocks:
    ......@@ -162,7 +162,7 @@ drivers:
    i2c_slave_amode: Mask
    i2c_slave_gencen: false
    i2c_slave_lowtout: false
    i2c_slave_runstdby: false
    i2c_slave_runstdby: true
    i2c_slave_sclsm: false
    i2c_slave_sdahold: 300-600ns hold time
    i2c_slave_sexttoen: false
    ......@@ -181,7 +181,7 @@ drivers:
    domain_group:
    nodes:
    - name: Core
    input: Generic clock generator 0
    input: Generic clock generator 4
    external: false
    external_frequency: 0
    - name: Slow
    ......@@ -189,7 +189,7 @@ drivers:
    external: false
    external_frequency: 0
    configuration:
    core_gclk_selection: Generic clock generator 0
    core_gclk_selection: Generic clock generator 4
    slow_gclk_selection: Generic clock generator 3
    DMAC:
    user_label: DMAC
    ......@@ -477,14 +477,14 @@ drivers:
    functionality: System
    api: HAL:HPL:SYSCTRL
    configuration:
    $input: 31250
    $input_id: Generic clock generator 1
    RESERVED_InputFreq: 31250
    RESERVED_InputFreq_id: Generic clock generator 1
    _$freq_output_8MHz Internal Oscillator (OSC8M): 1000000
    $input: 31007.751937984496
    $input_id: External Crystal Oscillator 0.4-32MHz (XOSC)
    RESERVED_InputFreq: 31007.751937984496
    RESERVED_InputFreq_id: External Crystal Oscillator 0.4-32MHz (XOSC)
    _$freq_output_8MHz Internal Oscillator (OSC8M): 8000000
    _$freq_output_Digital Frequency Locked Loop (DFLL48M): 48000000
    _$freq_output_External Crystal Oscillator 0.4-32MHz (XOSC): 400000
    _$freq_output_Fractional Digital Phase Locked Loop (FDPLL96M): 45775390.625
    _$freq_output_External Crystal Oscillator 0.4-32MHz (XOSC): '8000000'
    _$freq_output_Fractional Digital Phase Locked Loop (FDPLL96M): 186046.511627907
    dfll48m_arch_bplckc: false
    dfll48m_arch_calibration: false
    dfll48m_arch_ccdis: true
    ......@@ -494,12 +494,12 @@ drivers:
    dfll48m_arch_llaw: false
    dfll48m_arch_ondemand: false
    dfll48m_arch_qldis: false
    dfll48m_arch_runstdby: false
    dfll48m_arch_runstdby: true
    dfll48m_arch_stable: false
    dfll48m_arch_usbcrm: true
    dfll48m_arch_waitlock: false
    dfll48m_arch_usbcrm: false
    dfll48m_arch_waitlock: true
    dfll48m_mode: Closed Loop Mode
    dfll48m_mul: 48000
    dfll48m_mul: 1536
    dfll48m_ref_clock: Generic clock generator 1
    dfll_arch_cstep: 3
    dfll_arch_fstep: 31
    ......@@ -514,10 +514,10 @@ drivers:
    fdpll96m_arch_lbypass: true
    fdpll96m_arch_ondemand: false
    fdpll96m_arch_runstdby: false
    fdpll96m_clock_div: 1
    fdpll96m_ldr: 1463
    fdpll96m_ldrfrac: 13
    fdpll96m_ref_clock: Generic clock generator 1
    fdpll96m_clock_div: 128
    fdpll96m_ldr: 5
    fdpll96m_ldrfrac: 0
    fdpll96m_ref_clock: External Crystal Oscillator 0.4-32MHz (XOSC)
    osc32k_arch_calib: 0
    osc32k_arch_en1k: false
    osc32k_arch_en32k: false
    ......@@ -531,8 +531,8 @@ drivers:
    osc8m_arch_enable: true
    osc8m_arch_ondemand: true
    osc8m_arch_overwrite_calibration: false
    osc8m_arch_runstdby: false
    osc8m_presc: '8'
    osc8m_arch_runstdby: true
    osc8m_presc: '1'
    osculp32k_arch_calib: 0
    osculp32k_arch_overwrite_calibration: false
    osculp32k_arch_wrtlock: false
    ......@@ -545,14 +545,14 @@ drivers:
    xosc32k_arch_startup: 122 us
    xosc32k_arch_wrtlock: false
    xosc32k_arch_xtalen: true
    xosc_arch_ampgc: false
    xosc_arch_ampgc: true
    xosc_arch_enable: false
    xosc_arch_gain: 2Mhz
    xosc_arch_ondemand: true
    xosc_arch_runstdby: false
    xosc_arch_startup: 31 us
    xosc_arch_xtalen: false
    xosc_frequency: 400000
    xosc_arch_gain: 8Mhz
    xosc_arch_ondemand: false
    xosc_arch_runstdby: true
    xosc_arch_startup: 125000 us
    xosc_arch_xtalen: true
    xosc_frequency: 8000000
    optional_signals: []
    variant: null
    clocks:
    ......@@ -575,18 +575,21 @@ pads:
    definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA20
    mode: Digital input
    user_label: ADDR1
    configuration: null
    configuration:
    pad_pull_config: Pull-up
    ADDR2:
    name: PA21
    definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA21
    mode: Digital input
    user_label: ADDR2
    configuration: null
    configuration:
    pad_pull_config: Pull-up
    ADDR0:
    name: PB22
    definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PB22
    mode: Digital input
    user_label: ADDR0
    configuration: null
    configuration:
    pad_pull_config: Pull-up
    toolchain_options: []
    static_files: []
    bootloader/atmel_start_prj/config/hpl_gclk_config.h
    View file @ 165bfb65
    ......@@ -16,7 +16,7 @@
    // <i> Indicates whether Run in Standby is enabled or not
    // <id> gclk_arch_gen_0_RUNSTDBY
    #ifndef CONF_GCLK_GEN_0_RUNSTDBY
    #define CONF_GCLK_GEN_0_RUNSTDBY 0
    #define CONF_GCLK_GEN_0_RUNSTDBY 1
    #endif
    // <q> Divide Selection
    ......@@ -151,7 +151,7 @@
    // <i>
    // <id> gclk_gen_1_div
    #ifndef CONF_GCLK_GEN_1_DIV
    #define CONF_GCLK_GEN_1_DIV 32
    #define CONF_GCLK_GEN_1_DIV 256
    #endif
    // </h>
    ......@@ -167,7 +167,7 @@
    // <i> Indicates whether Run in Standby is enabled or not
    // <id> gclk_arch_gen_2_RUNSTDBY
    #ifndef CONF_GCLK_GEN_2_RUNSTDBY
    #define CONF_GCLK_GEN_2_RUNSTDBY 0
    #define CONF_GCLK_GEN_2_RUNSTDBY 1
    #endif
    // <q> Divide Selection
    ......@@ -202,7 +202,7 @@
    // <i> Indicates whether Generic Clock Generator Enable is enabled or not
    // <id> gclk_arch_gen_2_enable
    #ifndef CONF_GCLK_GEN_2_GENEN
    #define CONF_GCLK_GEN_2_GENEN 0
    #define CONF_GCLK_GEN_2_GENEN 1
    #endif
    // <y> Generic clock generator 2 source
    ......@@ -243,7 +243,7 @@
    // <i> Indicates whether Run in Standby is enabled or not
    // <id> gclk_arch_gen_3_RUNSTDBY
    #ifndef CONF_GCLK_GEN_3_RUNSTDBY
    #define CONF_GCLK_GEN_3_RUNSTDBY 0
    #define CONF_GCLK_GEN_3_RUNSTDBY 1
    #endif
    // <q> Divide Selection
    ......@@ -311,7 +311,7 @@
    // <i> Indicates whether generic clock 4 configuration is enabled or not
    // <id> enable_gclk_gen_4
    #ifndef CONF_GCLK_GENERATOR_4_CONFIG
    #define CONF_GCLK_GENERATOR_4_CONFIG 0
    #define CONF_GCLK_GENERATOR_4_CONFIG 1
    #endif
    // <h> Generic Clock Generator Control
    ......@@ -319,7 +319,7 @@
    // <i> Indicates whether Run in Standby is enabled or not
    // <id> gclk_arch_gen_4_RUNSTDBY
    #ifndef CONF_GCLK_GEN_4_RUNSTDBY
    #define CONF_GCLK_GEN_4_RUNSTDBY 0
    #define CONF_GCLK_GEN_4_RUNSTDBY 1
    #endif
    // <q> Divide Selection
    ......@@ -354,7 +354,7 @@
    // <i> Indicates whether Generic Clock Generator Enable is enabled or not
    // <id> gclk_arch_gen_4_enable
    #ifndef CONF_GCLK_GEN_4_GENEN
    #define CONF_GCLK_GEN_4_GENEN 0
    #define CONF_GCLK_GEN_4_GENEN 1
    #endif
    // <y> Generic clock generator 4 source
    ......@@ -370,7 +370,7 @@
    // <i> This defines the clock source for generic clock generator 4
    // <id> gclk_gen_4_oscillator
    #ifndef CONF_GCLK_GEN_4_SRC
    #define CONF_GCLK_GEN_4_SRC GCLK_GENCTRL_SRC_XOSC
    #define CONF_GCLK_GEN_4_SRC GCLK_GENCTRL_SRC_DFLL48M
    #endif
    // </h>
    ......@@ -379,7 +379,7 @@
    // <i>
    // <id> gclk_gen_4_div
    #ifndef CONF_GCLK_GEN_4_DIV
    #define CONF_GCLK_GEN_4_DIV 1
    #define CONF_GCLK_GEN_4_DIV 6
    #endif
    // </h>
    ......
    bootloader/atmel_start_prj/config/hpl_pm_config.h
    View file @ 165bfb65
    ......@@ -59,7 +59,7 @@
    // <15=> 15
    // <id> nvm_wait_states
    #ifndef CONF_NVM_WAIT_STATE
    #define CONF_NVM_WAIT_STATE 1
    #define CONF_NVM_WAIT_STATE 0
    #endif
    // </h>
    ......
    bootloader/atmel_start_prj/config/hpl_sercom_config.h
    View file @ 165bfb65
    ......@@ -35,7 +35,7 @@
    // <i> Determine if the module shall run in standby sleep mode
    // <id> i2c_slave_runstdby
    #ifndef CONF_SERCOM_2_I2CS_RUNSTDBY
    #define CONF_SERCOM_2_I2CS_RUNSTDBY 0
    #define CONF_SERCOM_2_I2CS_RUNSTDBY 1
    #endif
    // <o> SDA Hold Time (SDAHOLD)
    ......
    bootloader/atmel_start_prj/config/hpl_sysctrl_config.h
    View file @ 165bfb65
    ......@@ -72,7 +72,7 @@
    // <i> If this bit is 1: The oscillator is not stopped in standby sleep mode.
    // <id> osc8m_arch_runstdby
    #ifndef CONF_OSC8M_RUNSTDBY
    #define CONF_OSC8M_RUNSTDBY 0
    #define CONF_OSC8M_RUNSTDBY 1
    #endif
    // <y> Prescaler
    ......@@ -84,7 +84,7 @@
    // <i> Default: No Prescaling
    // <id> osc8m_presc
    #ifndef CONF_OSC8M_PRESC
    #define CONF_OSC8M_PRESC SYSCTRL_OSC8M_PRESC_3_Val
    #define CONF_OSC8M_PRESC SYSCTRL_OSC8M_PRESC_0_Val
    #endif
    // <q> Overwrite Default Osc Calibration
    ......@@ -291,7 +291,7 @@
    // <i> Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator.
    // <id> xosc_frequency
    #ifndef CONF_XOSC_FREQUENCY
    #define CONF_XOSC_FREQUENCY 400000
    #define CONF_XOSC_FREQUENCY 8000000
    #endif
    // <h> External Multipurpose Crystal Oscillator (XOSC) Control
    ......@@ -308,7 +308,7 @@
    // <i> If this bit is 1: the oscillator will only be running when requested by a peripheral.
    // <id> xosc_arch_ondemand
    #ifndef CONF_XOSC_ONDEMAND
    #define CONF_XOSC_ONDEMAND 1
    #define CONF_XOSC_ONDEMAND 0
    #endif
    // <q> Run In Standby
    ......@@ -317,21 +317,21 @@
    // <i> If this bit is 1: The oscillator is not stopped in standby sleep mode.
    // <id> xosc_arch_runstdby
    #ifndef CONF_XOSC_RUNSTDBY
    #define CONF_XOSC_RUNSTDBY 0
    #define CONF_XOSC_RUNSTDBY 1
    #endif
    // <q> Enable XTAL
    // <i> Enable XTAL
    // <id> xosc_arch_xtalen
    #ifndef CONF_XOSC_XTALEN
    #define CONF_XOSC_XTALEN 0
    #define CONF_XOSC_XTALEN 1
    #endif
    // <q> Automatic Amplitude Control Enable
    // <i> Indicates whether Automatic Amplitude Control is Enabled or not
    // <id> xosc_arch_ampgc
    #ifndef CONF_XOSC_AMPGC
    #define CONF_XOSC_AMPGC 0
    #define CONF_XOSC_AMPGC 1
    #endif
    // <y> Gain of the Oscillator
    ......@@ -343,7 +343,7 @@
    // <i> Select the Gain of the oscillator
    // <id> xosc_arch_gain
    #ifndef CONF_XOSC_GAIN
    #define CONF_XOSC_GAIN SYSCTRL_XOSC_GAIN_0_Val
    #define CONF_XOSC_GAIN SYSCTRL_XOSC_GAIN_2_Val
    #endif
    // <y> Start up time for the External Oscillator
    ......@@ -367,7 +367,7 @@
    // <i> Default: 31 us
    // <id> xosc_arch_startup
    #ifndef CONF_XOSC_STARTUP
    #define CONF_XOSC_STARTUP CONF_XOSC_STARTUP_TIME_31MCS
    #define CONF_XOSC_STARTUP CONF_XOSC_STARTUP_TIME_125000MCS
    #endif
    // </h>
    ......@@ -440,7 +440,7 @@
    // <i> Indicates whether Wait Lock is Enables or not
    // <id> dfll48m_arch_waitlock
    #ifndef CONF_DFLL_WAITLOCK
    #define CONF_DFLL_WAITLOCK 0
    #define CONF_DFLL_WAITLOCK 1
    #endif
    // <q> Bypass Coarse Lock
    ......@@ -479,14 +479,14 @@
    // <i> If this bit is 1: The DFLL is not stopped in standby sleep mode.
    // <id> dfll48m_arch_runstdby
    #ifndef CONF_DFLL_RUNSTDBY
    #define CONF_DFLL_RUNSTDBY 0
    #define CONF_DFLL_RUNSTDBY 1
    #endif
    // <q> USB Clock Recovery Mode
    // <i> USB Clock Recovery Mode
    // <id> dfll48m_arch_usbcrm
    #ifndef CONF_DFLL_USBCRM
    #define CONF_DFLL_USBCRM 1
    #define CONF_DFLL_USBCRM 0
    #endif
    #if CONF_DFLL_USBCRM == 1
    ......@@ -540,7 +540,7 @@
    // <i> Default: 0
    // <id> dfll48m_mul
    #ifndef CONF_DFLL_MUL
    #define CONF_DFLL_MUL 48000
    #define CONF_DFLL_MUL 1536
    #endif
    // <e> DFLL Calibration Overwrite
    ......@@ -600,7 +600,7 @@
    // <i> Select the clock source.
    // <id> fdpll96m_ref_clock
    #ifndef CONF_DPLL_GCLK
    #define CONF_DPLL_GCLK GCLK_CLKCTRL_GEN_GCLK1_Val
    #define CONF_DPLL_GCLK GCLK_GENCTRL_SRC_XOSC
    #endif
    #if (CONF_DPLL_GCLK == GCLK_GENCTRL_SRC_XOSC32K)
    ......@@ -648,21 +648,21 @@
    // <i> Clock Division Factor (Applicable if reference clock is XOSC)
    // <id> fdpll96m_clock_div
    #ifndef CONF_DPLL_DIV
    #define CONF_DPLL_DIV 1
    #define CONF_DPLL_DIV 128
    #endif
    // <o>DPLL LDRFRAC<0-15>
    // <i> Set the fractional part of the frequency multiplier.
    // <id> fdpll96m_ldrfrac
    #ifndef CONF_DPLL_LDRFRAC
    #define CONF_DPLL_LDRFRAC 13
    #define CONF_DPLL_LDRFRAC 0
    #endif
    // <o>DPLL LDR <0-4095>
    // <i> Set the integer part of the frequency multiplier.
    // <id> fdpll96m_ldr
    #ifndef CONF_DPLL_LDR
    #define CONF_DPLL_LDR 1463
    #define CONF_DPLL_LDR 5
    #endif
    // </h>
    ......
    bootloader/atmel_start_prj/config/peripheral_clk_config.h
    View file @ 165bfb65
    ......@@ -33,7 +33,7 @@
    // <i> Select the clock source for CORE.
    #ifndef CONF_GCLK_SERCOM2_CORE_SRC
    #define CONF_GCLK_SERCOM2_CORE_SRC GCLK_CLKCTRL_GEN_GCLK0_Val
    #define CONF_GCLK_SERCOM2_CORE_SRC GCLK_CLKCTRL_GEN_GCLK4_Val
    #endif
    // <y> Slow Clock Source
    ......@@ -65,7 +65,7 @@
    * \brief SERCOM2's Core Clock frequency
    */
    #ifndef CONF_GCLK_SERCOM2_CORE_FREQUENCY
    #define CONF_GCLK_SERCOM2_CORE_FREQUENCY 24000000
    #define CONF_GCLK_SERCOM2_CORE_FREQUENCY 8000000
    #endif
    /**
    ......
    bootloader/atmel_start_prj/driver_init.c
    View file @ 165bfb65
    ......@@ -69,7 +69,7 @@ void system_init(void)
    // <GPIO_PULL_OFF"> Off
    // <GPIO_PULL_UP"> Pull-up
    // <GPIO_PULL_DOWN"> Pull-down
    GPIO_PULL_OFF);
    GPIO_PULL_UP);
    gpio_set_pin_function(ADDR1, GPIO_PIN_FUNCTION_OFF);
    ......@@ -84,7 +84,7 @@ void system_init(void)
    // <GPIO_PULL_OFF"> Off
    // <GPIO_PULL_UP"> Pull-up
    // <GPIO_PULL_DOWN"> Pull-down
    GPIO_PULL_OFF);
    GPIO_PULL_UP);
    gpio_set_pin_function(ADDR2, GPIO_PIN_FUNCTION_OFF);
    ......@@ -99,7 +99,7 @@ void system_init(void)
    // <GPIO_PULL_OFF"> Off
    // <GPIO_PULL_UP"> Pull-up
    // <GPIO_PULL_DOWN"> Pull-down
    GPIO_PULL_OFF);
    GPIO_PULL_UP);
    gpio_set_pin_function(ADDR0, GPIO_PIN_FUNCTION_OFF);
    ......
    bootloader/atmel_start_prj/gcc/Makefile 0 → 100644
    View file @ 165bfb65
    ################################################################################
    # Automatically-generated file. Do not edit!
    ################################################################################
    ifdef SystemRoot
    SHELL = cmd.exe
    MK_DIR = mkdir
    else
    ifeq ($(shell uname), Linux)
    MK_DIR = mkdir -p
    endif
    ifeq ($(shell uname | cut -d _ -f 1), CYGWIN)
    MK_DIR = mkdir -p
    endif
    ifeq ($(shell uname | cut -d _ -f 1), MINGW32)
    MK_DIR = mkdir -p
    endif
    ifeq ($(shell uname | cut -d _ -f 1), MINGW64)
    MK_DIR = mkdir -p
    endif
    ifeq ($(shell uname | cut -d _ -f 1), DARWIN)
    MK_DIR = mkdir -p
    endif
    endif
    # List the subdirectories for creating object files
    SUB_DIRS += \
    \
    samd21a/gcc/gcc \
    hpl/dmac \
    hal/src \
    samd21a/gcc \
    hpl/pm \
    hpl/sysctrl \
    hal/utils/src \
    hpl/sercom \
    examples \
    hpl/gclk \
    hpl/core
    # List the object files
    OBJS += \
    hal/src/hal_io.o \
    samd21a/gcc/gcc/startup_samd21.o \
    hal/src/hal_i2c_s_async.o \
    hal/utils/src/utils_syscalls.o \
    hal/src/hal_delay.o \
    hpl/pm/hpl_pm.o \
    hpl/core/hpl_init.o \
    hal/utils/src/utils_list.o \
    hpl/core/hpl_core_m0plus_base.o \
    hal/utils/src/utils_assert.o \
    hpl/dmac/hpl_dmac.o \
    hpl/sysctrl/hpl_sysctrl.o \
    hpl/gclk/hpl_gclk.o \
    hal/src/hal_init.o \
    main.o \
    samd21a/gcc/system_samd21.o \
    examples/driver_examples.o \
    driver_init.o \
    hpl/sercom/hpl_sercom.o \
    hal/utils/src/utils_ringbuffer.o \
    hal/src/hal_gpio.o \
    hal/utils/src/utils_event.o \
    hal/src/hal_sleep.o \
    atmel_start.o \
    hal/src/hal_atomic.o
    OBJS_AS_ARGS += \
    "hal/src/hal_io.o" \
    "samd21a/gcc/gcc/startup_samd21.o" \
    "hal/src/hal_i2c_s_async.o" \
    "hal/utils/src/utils_syscalls.o" \
    "hal/src/hal_delay.o" \
    "hpl/pm/hpl_pm.o" \
    "hpl/core/hpl_init.o" \
    "hal/utils/src/utils_list.o" \
    "hpl/core/hpl_core_m0plus_base.o" \
    "hal/utils/src/utils_assert.o" \
    "hpl/dmac/hpl_dmac.o" \
    "hpl/sysctrl/hpl_sysctrl.o" \
    "hpl/gclk/hpl_gclk.o" \
    "hal/src/hal_init.o" \
    "main.o" \
    "samd21a/gcc/system_samd21.o" \
    "examples/driver_examples.o" \
    "driver_init.o" \
    "hpl/sercom/hpl_sercom.o" \
    "hal/utils/src/utils_ringbuffer.o" \
    "hal/src/hal_gpio.o" \
    "hal/utils/src/utils_event.o" \
    "hal/src/hal_sleep.o" \
    "atmel_start.o" \
    "hal/src/hal_atomic.o"
    # List the directories containing header files
    DIR_INCLUDES += \
    -I"../" \
    -I"../config" \
    -I"../examples" \
    -I"../hal/include" \
    -I"../hal/utils/include" \
    -I"../hpl/core" \
    -I"../hpl/dmac" \
    -I"../hpl/gclk" \
    -I"../hpl/pm" \
    -I"../hpl/port" \
    -I"../hpl/sercom" \
    -I"../hpl/sysctrl" \
    -I"../hri" \
    -I"../" \
    -I"../CMSIS/Core/Include" \
    -I"../samd21a/include"
    # List the dependency files
    DEPS := $(OBJS:%.o=%.d)
    DEPS_AS_ARGS += \
    "samd21a/gcc/gcc/startup_samd21.d" \
    "hal/src/hal_gpio.d" \
    "hal/src/hal_io.d" \
    "hal/src/hal_i2c_s_async.d" \
    "hal/utils/src/utils_syscalls.d" \
    "hpl/core/hpl_core_m0plus_base.d" \
    "hal/utils/src/utils_list.d" \
    "hpl/dmac/hpl_dmac.d" \
    "hal/utils/src/utils_assert.d" \
    "hal/src/hal_delay.d" \
    "hpl/core/hpl_init.d" \
    "hpl/sysctrl/hpl_sysctrl.d" \
    "hpl/gclk/hpl_gclk.d" \
    "hal/src/hal_init.d" \
    "driver_init.d" \
    "samd21a/gcc/system_samd21.d" \
    "main.d" \
    "examples/driver_examples.d" \
    "hal/src/hal_sleep.d" \
    "hal/utils/src/utils_ringbuffer.d" \
    "hpl/sercom/hpl_sercom.d" \
    "hal/utils/src/utils_event.d" \
    "hal/src/hal_atomic.d" \
    "hpl/pm/hpl_pm.d" \
    "atmel_start.d"
    OUTPUT_FILE_NAME :=AtmelStart
    QUOTE := "
    OUTPUT_FILE_PATH +=$(OUTPUT_FILE_NAME).elf
    OUTPUT_FILE_PATH_AS_ARGS +=$(OUTPUT_FILE_NAME).elf
    vpath %.c ../
    vpath %.s ../
    vpath %.S ../
    # All Target
    all: $(SUB_DIRS) $(OUTPUT_FILE_PATH)
    # Linker target
    $(OUTPUT_FILE_PATH): $(OBJS)
    @echo Building target: $@
    @echo Invoking: ARM/GNU Linker
    $(QUOTE)arm-none-eabi-gcc$(QUOTE) -o $(OUTPUT_FILE_NAME).elf $(OBJS_AS_ARGS) -Wl,--start-group -lm -Wl,--end-group -mthumb \
    -Wl,-Map="$(OUTPUT_FILE_NAME).map" --specs=nano.specs -Wl,--gc-sections -mcpu=cortex-m0plus \
    \
    -T"../samd21a/gcc/gcc/samd21g18a_flash.ld" \
    -L"../samd21a/gcc/gcc"
    @echo Finished building target: $@
    "arm-none-eabi-objcopy" -O binary "$(OUTPUT_FILE_NAME).elf" "$(OUTPUT_FILE_NAME).bin"
    "arm-none-eabi-objcopy" -O ihex -R .eeprom -R .fuse -R .lock -R .signature \
    "$(OUTPUT_FILE_NAME).elf" "$(OUTPUT_FILE_NAME).hex"
    "arm-none-eabi-objcopy" -j .eeprom --set-section-flags=.eeprom=alloc,load --change-section-lma \
    .eeprom=0 --no-change-warnings -O binary "$(OUTPUT_FILE_NAME).elf" \
    "$(OUTPUT_FILE_NAME).eep" || exit 0
    "arm-none-eabi-objdump" -h -S "$(OUTPUT_FILE_NAME).elf" > "$(OUTPUT_FILE_NAME).lss"
    "arm-none-eabi-size" "$(OUTPUT_FILE_NAME).elf"
    # Compiler targets
    %.o: %.c
    @echo Building file: $<
    @echo ARM/GNU C Compiler
    $(QUOTE)arm-none-eabi-gcc$(QUOTE) -x c -mthumb -DDEBUG -Os -ffunction-sections -mlong-calls -g3 -Wall -c -std=gnu99 \
    -D__SAMD21G18A__ -mcpu=cortex-m0plus \
    $(DIR_INCLUDES) \
    -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
    @echo Finished building: $<
    %.o: %.s
    @echo Building file: $<
    @echo ARM/GNU Assembler
    $(QUOTE)arm-none-eabi-as$(QUOTE) -x c -mthumb -DDEBUG -Os -ffunction-sections -mlong-calls -g3 -Wall -c -std=gnu99 \
    -D__SAMD21G18A__ -mcpu=cortex-m0plus \
    $(DIR_INCLUDES) \
    -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
    @echo Finished building: $<
    %.o: %.S
    @echo Building file: $<
    @echo ARM/GNU Preprocessing Assembler
    $(QUOTE)arm-none-eabi-gcc$(QUOTE) -x c -mthumb -DDEBUG -Os -ffunction-sections -mlong-calls -g3 -Wall -c -std=gnu99 \
    -D__SAMD21G18A__ -mcpu=cortex-m0plus \
    $(DIR_INCLUDES) \
    -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
    @echo Finished building: $<
    # Detect changes in the dependent files and recompile the respective object files.
    ifneq ($(MAKECMDGOALS),clean)
    ifneq ($(strip $(DEPS)),)
    -include $(DEPS)
    endif
    endif
    $(SUB_DIRS):
    $(MK_DIR) "$@"
    clean:
    rm -f $(OBJS_AS_ARGS)
    rm -f $(OUTPUT_FILE_PATH)
    rm -f $(DEPS_AS_ARGS)
    rm -f $(OUTPUT_FILE_NAME).a $(OUTPUT_FILE_NAME).hex $(OUTPUT_FILE_NAME).bin \
    $(OUTPUT_FILE_NAME).lss $(OUTPUT_FILE_NAME).eep $(OUTPUT_FILE_NAME).map \
    $(OUTPUT_FILE_NAME).srec
    \ No newline at end of file
    bootloader/atmel_start_prj/hpl/core/hpl_init.c
    View file @ 165bfb65
    ......@@ -41,10 +41,11 @@
    #include <hpl_dmac_config.h>
    /* Referenced GCLKs (out of 0~7), should be initialized firstly
    * - GCLK 1 for DFLL48M
    */
    #define _GCLK_INIT_1ST 0x00000000
    #define _GCLK_INIT_1ST 0x00000002
    /* Not referenced GCLKs, initialized last */
    #define _GCLK_INIT_LAST 0x000000FF
    #define _GCLK_INIT_LAST 0x000000FD
    /**
    * \brief Initialize the hardware abstraction layer
    ......
    bootloader/atmel_start_prj/hpl/sercom/hpl_sercom.c
    View file @ 165bfb65
    ......@@ -1719,10 +1719,6 @@ int32_t _i2c_s_async_init(struct _i2c_s_async_device *const device, void *const
    NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(hw));
    NVIC_EnableIRQ((IRQn_Type)_sercom_get_irq_num(hw));
    // Enable Address Match and PREC interrupt by default.
    hri_sercomi2cs_set_INTEN_AMATCH_bit(hw);
    hri_sercomi2cs_set_INTEN_PREC_bit(hw);
    return ERR_NONE;
    }
    ......@@ -1925,14 +1921,7 @@ static void _sercom_i2c_s_irq_handler(struct _i2c_s_async_device *device)
    if (flags & SERCOM_I2CS_INTFLAG_ERROR) {
    ASSERT(device->cb.error);
    device->cb.error(device);
    }
    if (flags & SERCOM_I2CS_INTFLAG_AMATCH) {
    hri_sercomi2cs_clear_INTFLAG_AMATCH_bit(hw);
    }
    if (flags & SERCOM_I2CS_INTFLAG_PREC) {
    hri_sercomi2cs_clear_INTFLAG_PREC_bit(hw);
    }
    if (flags & SERCOM_I2CS_INTFLAG_DRDY) {
    } else if (flags & SERCOM_I2CS_INTFLAG_DRDY) {
    if (!hri_sercomi2cs_get_STATUS_DIR_bit(hw)) {
    ASSERT(device->cb.rx_done);
    device->cb.rx_done(device, hri_sercomi2cs_read_DATA_reg(hw));
    ......@@ -1940,7 +1929,6 @@ static void _sercom_i2c_s_irq_handler(struct _i2c_s_async_device *device)
    ASSERT(device->cb.tx);
    device->cb.tx(device);
    }
    hri_sercomi2cs_clear_INTFLAG_DRDY_bit(hw);
    #if (CONF_MCLK_LPDIV) != (CONF_MCLK_CPUDIV)
    /* Adding grace time while waiting for SCL line to be released */
    hri_sercomi2cs_clear_STATUS_reg(hw, 0);
    ......
    bootloader/atmel_start_prj/samd21a/include/component-version.h
    View file @ 165bfb65
    /**
    * \file
    *
    * \brief Component version header file
    *
    * Copyright (c) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
    *
    * \license_start
    *
    * \page License
    *
    * Licensed under the Apache License, Version 2.0 (the "License");
    * you may not use this file except in compliance with the License.
    * You may obtain a copy of the License at
    *
    * http://www.apache.org/licenses/LICENSE-2.0
    *
    * Unless required by applicable law or agreed to in writing, software
    * distributed under the License is distributed on an "AS IS" BASIS,
    * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
    * See the License for the specific language governing permissions and
    * limitations under the License.
    *
    * \license_stop
    *
    */
    #ifndef _COMPONENT_VERSION_H_INCLUDED
    #define _COMPONENT_VERSION_H_INCLUDED
    #define COMPONENT_VERSION_MAJOR 1
    #define COMPONENT_VERSION_MINOR 3
    //
    // The COMPONENT_VERSION define is composed of the major and the minor version number.
    //
    // The last four digits of the COMPONENT_VERSION is the minor version with leading zeros.
    // The rest of the COMPONENT_VERSION is the major version.
    //
    #define COMPONENT_VERSION 10003
    //
    // The build number does not refer to the component, but to the build number
    // of the device pack that provides the component.
    //
    #define BUILD_NUMBER 395
    //
    // The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding.
    //
    #define COMPONENT_VERSION_STRING "1.3"
    //
    // The COMPONENT_DATE_STRING contains a timestamp of when the pack was generated.
    //
    // The COMPONENT_DATE_STRING is written out using the following strftime pattern.
    //
    // "%Y-%m-%d %H:%M:%S"
    //
    //
    #define COMPONENT_DATE_STRING "2019-09-19 13:04:38"
    #endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */
    /**
    * \file
    *
    * \brief Component version header file
    *
    * Copyright (c) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
    *
    * \license_start
    *
    * \page License
    *
    * Licensed under the Apache License, Version 2.0 (the "License");
    * you may not use this file except in compliance with the License.
    * You may obtain a copy of the License at
    *
    * http://www.apache.org/licenses/LICENSE-2.0
    *
    * Unless required by applicable law or agreed to in writing, software
    * distributed under the License is distributed on an "AS IS" BASIS,
    * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
    * See the License for the specific language governing permissions and
    * limitations under the License.
    *
    * \license_stop
    *
    */
    #ifndef _COMPONENT_VERSION_H_INCLUDED
    #define _COMPONENT_VERSION_H_INCLUDED
    #define COMPONENT_VERSION_MAJOR 1
    #define COMPONENT_VERSION_MINOR 3
    //
    // The COMPONENT_VERSION define is composed of the major and the minor version number.
    //
    // The last four digits of the COMPONENT_VERSION is the minor version with leading zeros.
    // The rest of the COMPONENT_VERSION is the major version.
    //
    #define COMPONENT_VERSION 10003
    //
    // The build number does not refer to the component, but to the build number
    // of the device pack that provides the component.
    //
    #define BUILD_NUMBER 395
    //
    // The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding.
    //
    #define COMPONENT_VERSION_STRING "1.3"
    //
    // The COMPONENT_DATE_STRING contains a timestamp of when the pack was generated.
    //
    // The COMPONENT_DATE_STRING is written out using the following strftime pattern.
    //
    // "%Y-%m-%d %H:%M:%S"
    //
    //
    #define COMPONENT_DATE_STRING "2019-09-19 13:04:38"
    #endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */
    bootloader/atmel_start_prj/samd21a/include/component/hmatrixb.h
    View file @ 165bfb65
    /**
    * \file
    *
    * \brief Component description for HMATRIXB
    *
    * Copyright (c) 2018 Microchip Technology Inc.
    *
    * \asf_license_start
    *
    * \page License
    *
    * SPDX-License-Identifier: Apache-2.0
    *
    * Licensed under the Apache License, Version 2.0 (the "License"); you may
    * not use this file except in compliance with the License.
    * You may obtain a copy of the Licence at
    *
    * http://www.apache.org/licenses/LICENSE-2.0
    *
    * Unless required by applicable law or agreed to in writing, software
    * distributed under the License is distributed on an AS IS BASIS, WITHOUT
    * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
    * See the License for the specific language governing permissions and
    * limitations under the License.
    *
    * \asf_license_stop
    *
    */
    #ifndef _SAMD21_HMATRIXB_COMPONENT_
    #define _SAMD21_HMATRIXB_COMPONENT_
    /* ========================================================================== */
    /** SOFTWARE API DEFINITION FOR HMATRIXB */
    /* ========================================================================== */
    /** \addtogroup SAMD21_HMATRIXB HSB Matrix */
    /*@{*/
    #define HMATRIXB_I7638
    #define REV_HMATRIXB 0x212
    /* -------- HMATRIXB_PRAS : (HMATRIXB Offset: 0x080) (R/W 32) PRS Priority A for Slave -------- */
    #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
    typedef union {
    uint32_t reg; /*!< Type used for register access */
    } HMATRIXB_PRAS_Type;
    #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
    #define HMATRIXB_PRAS_OFFSET 0x080 /**< \brief (HMATRIXB_PRAS offset) Priority A for Slave */
    #define HMATRIXB_PRAS_RESETVALUE _U_(0x00000000) /**< \brief (HMATRIXB_PRAS reset_value) Priority A for Slave */
    #define HMATRIXB_PRAS_MASK _U_(0x00000000) /**< \brief (HMATRIXB_PRAS) MASK Register */
    /* -------- HMATRIXB_PRBS : (HMATRIXB Offset: 0x084) (R/W 32) PRS Priority B for Slave -------- */
    #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
    typedef union {
    uint32_t reg; /*!< Type used for register access */
    } HMATRIXB_PRBS_Type;
    #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
    #define HMATRIXB_PRBS_OFFSET 0x084 /**< \brief (HMATRIXB_PRBS offset) Priority B for Slave */
    #define HMATRIXB_PRBS_RESETVALUE _U_(0x00000000) /**< \brief (HMATRIXB_PRBS reset_value) Priority B for Slave */
    #define HMATRIXB_PRBS_MASK _U_(0x00000000) /**< \brief (HMATRIXB_PRBS) MASK Register */
    /* -------- HMATRIXB_SFR : (HMATRIXB Offset: 0x110) (R/W 32) Special Function -------- */
    #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
    typedef union {
    struct {
    uint32_t SFR:32; /*!< bit: 0..31 Special Function Register */
    } bit; /*!< Structure used for bit access */
    uint32_t reg; /*!< Type used for register access */
    } HMATRIXB_SFR_Type;
    #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
    #define HMATRIXB_SFR_OFFSET 0x110 /**< \brief (HMATRIXB_SFR offset) Special Function */
    #define HMATRIXB_SFR_RESETVALUE _U_(0x00000000) /**< \brief (HMATRIXB_SFR reset_value) Special Function */
    #define HMATRIXB_SFR_SFR_Pos 0 /**< \brief (HMATRIXB_SFR) Special Function Register */
    #define HMATRIXB_SFR_SFR_Msk (_U_(0xFFFFFFFF) << HMATRIXB_SFR_SFR_Pos)
    #define HMATRIXB_SFR_SFR(value) (HMATRIXB_SFR_SFR_Msk & ((value) << HMATRIXB_SFR_SFR_Pos))
    #define HMATRIXB_SFR_MASK _U_(0xFFFFFFFF) /**< \brief (HMATRIXB_SFR) MASK Register */
    /** \brief HmatrixbPrs hardware registers */
    #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
    typedef struct {
    __IO HMATRIXB_PRAS_Type PRAS; /**< \brief Offset: 0x000 (R/W 32) Priority A for Slave */
    __IO HMATRIXB_PRBS_Type PRBS; /**< \brief Offset: 0x004 (R/W 32) Priority B for Slave */
    } HmatrixbPrs;
    #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
    /** \brief HMATRIXB hardware registers */
    #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
    typedef struct {
    RoReg8 Reserved1[0x80];
    HmatrixbPrs Prs[16]; /**< \brief Offset: 0x080 HmatrixbPrs groups */
    RoReg8 Reserved2[0x10];
    __IO HMATRIXB_SFR_Type SFR[16]; /**< \brief Offset: 0x110 (R/W 32) Special Function */
    } Hmatrixb;
    #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
    /*@}*/
    #endif /* _SAMD21_HMATRIXB_COMPONENT_ */
    /**
    * \file
    *
    * \brief Component description for HMATRIXB
    *
    * Copyright (c) 2018 Microchip Technology Inc.
    *
    * \asf_license_start
    *
    * \page License
    *
    * SPDX-License-Identifier: Apache-2.0
    *
    * Licensed under the Apache License, Version 2.0 (the "License"); you may
    * not use this file except in compliance with the License.
    * You may obtain a copy of the Licence at
    *
    * http://www.apache.org/licenses/LICENSE-2.0
    *
    * Unless required by applicable law or agreed to in writing, software
    * distributed under the License is distributed on an AS IS BASIS, WITHOUT
    * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
    * See the License for the specific language governing permissions and
    * limitations under the License.
    *
    * \asf_license_stop
    *
    */
    #ifndef _SAMD21_HMATRIXB_COMPONENT_
    #define _SAMD21_HMATRIXB_COMPONENT_
    /* ========================================================================== */
    /** SOFTWARE API DEFINITION FOR HMATRIXB */
    /* ========================================================================== */
    /** \addtogroup SAMD21_HMATRIXB HSB Matrix */
    /*@{*/
    #define HMATRIXB_I7638
    #define REV_HMATRIXB 0x212
    /* -------- HMATRIXB_PRAS : (HMATRIXB Offset: 0x080) (R/W 32) PRS Priority A for Slave -------- */
    #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
    typedef union {
    uint32_t reg; /*!< Type used for register access */
    } HMATRIXB_PRAS_Type;
    #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
    #define HMATRIXB_PRAS_OFFSET 0x080 /**< \brief (HMATRIXB_PRAS offset) Priority A for Slave */
    #define HMATRIXB_PRAS_RESETVALUE _U_(0x00000000) /**< \brief (HMATRIXB_PRAS reset_value) Priority A for Slave */
    #define HMATRIXB_PRAS_MASK _U_(0x00000000) /**< \brief (HMATRIXB_PRAS) MASK Register */
    /* -------- HMATRIXB_PRBS : (HMATRIXB Offset: 0x084) (R/W 32) PRS Priority B for Slave -------- */
    #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
    typedef union {
    uint32_t reg; /*!< Type used for register access */
    } HMATRIXB_PRBS_Type;
    #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
    #define HMATRIXB_PRBS_OFFSET 0x084 /**< \brief (HMATRIXB_PRBS offset) Priority B for Slave */
    #define HMATRIXB_PRBS_RESETVALUE _U_(0x00000000) /**< \brief (HMATRIXB_PRBS reset_value) Priority B for Slave */
    #define HMATRIXB_PRBS_MASK _U_(0x00000000) /**< \brief (HMATRIXB_PRBS) MASK Register */
    /* -------- HMATRIXB_SFR : (HMATRIXB Offset: 0x110) (R/W 32) Special Function -------- */
    #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
    typedef union {
    struct {
    uint32_t SFR:32; /*!< bit: 0..31 Special Function Register */
    } bit; /*!< Structure used for bit access */
    uint32_t reg; /*!< Type used for register access */
    } HMATRIXB_SFR_Type;
    #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
    #define HMATRIXB_SFR_OFFSET 0x110 /**< \brief (HMATRIXB_SFR offset) Special Function */
    #define HMATRIXB_SFR_RESETVALUE _U_(0x00000000) /**< \brief (HMATRIXB_SFR reset_value) Special Function */
    #define HMATRIXB_SFR_SFR_Pos 0 /**< \brief (HMATRIXB_SFR) Special Function Register */
    #define HMATRIXB_SFR_SFR_Msk (_U_(0xFFFFFFFF) << HMATRIXB_SFR_SFR_Pos)
    #define HMATRIXB_SFR_SFR(value) (HMATRIXB_SFR_SFR_Msk & ((value) << HMATRIXB_SFR_SFR_Pos))
    #define HMATRIXB_SFR_MASK _U_(0xFFFFFFFF) /**< \brief (HMATRIXB_SFR) MASK Register */
    /** \brief HmatrixbPrs hardware registers */
    #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
    typedef struct {
    __IO HMATRIXB_PRAS_Type PRAS; /**< \brief Offset: 0x000 (R/W 32) Priority A for Slave */
    __IO HMATRIXB_PRBS_Type PRBS; /**< \brief Offset: 0x004 (R/W 32) Priority B for Slave */
    } HmatrixbPrs;
    #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
    /** \brief HMATRIXB hardware registers */
    #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
    typedef struct {
    RoReg8 Reserved1[0x80];
    HmatrixbPrs Prs[16]; /**< \brief Offset: 0x080 HmatrixbPrs groups */
    RoReg8 Reserved2[0x10];
    __IO HMATRIXB_SFR_Type SFR[16]; /**< \brief Offset: 0x110 (R/W 32) Special Function */
    } Hmatrixb;
    #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
    /*@}*/
    #endif /* _SAMD21_HMATRIXB_COMPONENT_ */
    bootloader/atmel_start_prj/samd21a/include/instance/ac.h
    View file @ 165bfb65
    /**
    * \file
    *
    * \brief Instance description for AC
    *
    * Copyright (c) 2018 Microchip Technology Inc.
    *
    * \asf_license_start
    *
    * \page License
    *
    * SPDX-License-Identifier: Apache-2.0
    *
    * Licensed under the Apache License, Version 2.0 (the "License"); you may
    * not use this file except in compliance with the License.
    * You may obtain a copy of the Licence at
    *
    * http://www.apache.org/licenses/LICENSE-2.0
    *
    * Unless required by applicable law or agreed to in writing, software
    * distributed under the License is distributed on an AS IS BASIS, WITHOUT
    * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
    * See the License for the specific language governing permissions and
    * limitations under the License.
    *
    * \asf_license_stop
    *
    */
    #ifndef _SAMD21_AC_INSTANCE_
    #define _SAMD21_AC_INSTANCE_
    /* ========== Register definition for AC peripheral ========== */
    #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
    #define REG_AC_CTRLA (0x42004400) /**< \brief (AC) Control A */
    #define REG_AC_CTRLB (0x42004401) /**< \brief (AC) Control B */
    #define REG_AC_EVCTRL (0x42004402) /**< \brief (AC) Event Control */
    #define REG_AC_INTENCLR (0x42004404) /**< \brief (AC) Interrupt Enable Clear */
    #define REG_AC_INTENSET (0x42004405) /**< \brief (AC) Interrupt Enable Set */
    #define REG_AC_INTFLAG (0x42004406) /**< \brief (AC) Interrupt Flag Status and Clear */
    #define REG_AC_STATUSA (0x42004408) /**< \brief (AC) Status A */
    #define REG_AC_STATUSB (0x42004409) /**< \brief (AC) Status B */
    #define REG_AC_STATUSC (0x4200440A) /**< \brief (AC) Status C */
    #define REG_AC_WINCTRL (0x4200440C) /**< \brief (AC) Window Control */
    #define REG_AC_COMPCTRL0 (0x42004410) /**< \brief (AC) Comparator Control 0 */
    #define REG_AC_COMPCTRL1 (0x42004414) /**< \brief (AC) Comparator Control 1 */
    #define REG_AC_SCALER0 (0x42004420) /**< \brief (AC) Scaler 0 */
    #define REG_AC_SCALER1 (0x42004421) /**< \brief (AC) Scaler 1 */
    #else
    #define REG_AC_CTRLA (*(RwReg8 *)0x42004400UL) /**< \brief (AC) Control A */
    #define REG_AC_CTRLB (*(WoReg8 *)0x42004401UL) /**< \brief (AC) Control B */
    #define REG_AC_EVCTRL (*(RwReg16*)0x42004402UL) /**< \brief (AC) Event Control */
    #define REG_AC_INTENCLR (*(RwReg8 *)0x42004404UL) /**< \brief (AC) Interrupt Enable Clear */
    #define REG_AC_INTENSET (*(RwReg8 *)0x42004405UL) /**< \brief (AC) Interrupt Enable Set */
    #define REG_AC_INTFLAG (*(RwReg8 *)0x42004406UL) /**< \brief (AC) Interrupt Flag Status and Clear */
    #define REG_AC_STATUSA (*(RoReg8 *)0x42004408UL) /**< \brief (AC) Status A */
    #define REG_AC_STATUSB (*(RoReg8 *)0x42004409UL) /**< \brief (AC) Status B */
    #define REG_AC_STATUSC (*(RoReg8 *)0x4200440AUL) /**< \brief (AC) Status C */
    #define REG_AC_WINCTRL (*(RwReg8 *)0x4200440CUL) /**< \brief (AC) Window Control */
    #define REG_AC_COMPCTRL0 (*(RwReg *)0x42004410UL) /**< \brief (AC) Comparator Control 0 */
    #define REG_AC_COMPCTRL1 (*(RwReg *)0x42004414UL) /**< \brief (AC) Comparator Control 1 */
    #define REG_AC_SCALER0 (*(RwReg8 *)0x42004420UL) /**< \brief (AC) Scaler 0 */
    #define REG_AC_SCALER1 (*(RwReg8 *)0x42004421UL) /**< \brief (AC) Scaler 1 */
    #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
    /* ========== Instance parameters for AC peripheral ========== */
    #define AC_CMP_NUM 2 // Number of comparators
    #define AC_GCLK_ID_ANA 32 // Index of Generic Clock for analog
    #define AC_GCLK_ID_DIG 31 // Index of Generic Clock for digital
    #define AC_NUM_CMP 2
    #define AC_PAIRS 1 // Number of pairs of comparators
    #endif /* _SAMD21_AC_INSTANCE_ */
    /**
    * \file
    *
    * \brief Instance description for AC
    *
    * Copyright (c) 2018 Microchip Technology Inc.
    *
    * \asf_license_start
    *
    * \page License
    *
    * SPDX-License-Identifier: Apache-2.0
    *
    * Licensed under the Apache License, Version 2.0 (the "License"); you may
    * not use this file except in compliance with the License.
    * You may obtain a copy of the Licence at
    *
    * http://www.apache.org/licenses/LICENSE-2.0
    *
    * Unless required by applicable law or agreed to in writing, software
    * distributed under the License is distributed on an AS IS BASIS, WITHOUT
    * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
    * See the License for the specific language governing permissions and
    * limitations under the License.
    *
    * \asf_license_stop
    *
    */
    #ifndef _SAMD21_AC_INSTANCE_
    #define _SAMD21_AC_INSTANCE_
    /* ========== Register definition for AC peripheral ========== */
    #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
    #define REG_AC_CTRLA (0x42004400) /**< \brief (AC) Control A */
    #define REG_AC_CTRLB (0x42004401) /**< \brief (AC) Control B */
    #define REG_AC_EVCTRL (0x42004402) /**< \brief (AC) Event Control */
    #define REG_AC_INTENCLR (0x42004404) /**< \brief (AC) Interrupt Enable Clear */
    #define REG_AC_INTENSET (0x42004405) /**< \brief (AC) Interrupt Enable Set */
    #define REG_AC_INTFLAG (0x42004406) /**< \brief (AC) Interrupt Flag Status and Clear */
    #define REG_AC_STATUSA (0x42004408) /**< \brief (AC) Status A */
    #define REG_AC_STATUSB (0x42004409) /**< \brief (AC) Status B */
    #define REG_AC_STATUSC (0x4200440A) /**< \brief (AC) Status C */
    #define REG_AC_WINCTRL (0x4200440C) /**< \brief (AC) Window Control */
    #define REG_AC_COMPCTRL0 (0x42004410) /**< \brief (AC) Comparator Control 0 */
    #define REG_AC_COMPCTRL1 (0x42004414) /**< \brief (AC) Comparator Control 1 */
    #define REG_AC_SCALER0 (0x42004420) /**< \brief (AC) Scaler 0 */
    #define REG_AC_SCALER1 (0x42004421) /**< \brief (AC) Scaler 1 */
    #else
    #define REG_AC_CTRLA (*(RwReg8 *)0x42004400UL) /**< \brief (AC) Control A */
    #define REG_AC_CTRLB (*(WoReg8 *)0x42004401UL) /**< \brief (AC) Control B */
    #define REG_AC_EVCTRL (*(RwReg16*)0x42004402UL) /**< \brief (AC) Event Control */
    #define REG_AC_INTENCLR (*(RwReg8 *)0x42004404UL) /**< \brief (AC) Interrupt Enable Clear */
    #define REG_AC_INTENSET (*(RwReg8 *)0x42004405UL) /**< \brief (AC) Interrupt Enable Set */
    #define REG_AC_INTFLAG (*(RwReg8 *)0x42004406UL) /**< \brief (AC) Interrupt Flag Status and Clear */
    #define REG_AC_STATUSA (*(RoReg8 *)0x42004408UL) /**< \brief (AC) Status A */
    #define REG_AC_STATUSB (*(RoReg8 *)0x42004409UL) /**< \brief (AC) Status B */
    #define REG_AC_STATUSC (*(RoReg8 *)0x4200440AUL) /**< \brief (AC) Status C */
    #define REG_AC_WINCTRL (*(RwReg8 *)0x4200440CUL) /**< \brief (AC) Window Control */
    #define REG_AC_COMPCTRL0 (*(RwReg *)0x42004410UL) /**< \brief (AC) Comparator Control 0 */
    #define REG_AC_COMPCTRL1 (*(RwReg *)0x42004414UL) /**< \brief (AC) Comparator Control 1 */
    #define REG_AC_SCALER0 (*(RwReg8 *)0x42004420UL) /**< \brief (AC) Scaler 0 */
    #define REG_AC_SCALER1 (*(RwReg8 *)0x42004421UL) /**< \brief (AC) Scaler 1 */
    #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
    /* ========== Instance parameters for AC peripheral ========== */
    #define AC_CMP_NUM 2 // Number of comparators
    #define AC_GCLK_ID_ANA 32 // Index of Generic Clock for analog
    #define AC_GCLK_ID_DIG 31 // Index of Generic Clock for digital
    #define AC_NUM_CMP 2
    #define AC_PAIRS 1 // Number of pairs of comparators
    #endif /* _SAMD21_AC_INSTANCE_ */
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