DI/OT main backplane v1
The DI/OT main backplane v1 is a KiCad design compatible with the CompactPCI Serial standard. It provides 9 slots (1 System Slot and 8 Peripheral Slots) and the support for RTMs.
DI/OT main backplane v1 (front view):
DI/OT main backplane v1 topology:
The backplane v1 provides:
- a star topology of 144 LVDS lanes in total (18 LVDS lanes per Peripheral Slot) used as differential or single-ended I/Os to implement communication between the System and Peripheral Boards. Out of those, 1 LVDS lane per Peripheral Slot is reserved for the distribution of low-jitter clock and 2 LVDS lanes are designated for high-speed communication
- the Reset line driven by the System Slot to reset all the Peripheral Boards
- a set of 5 multidrop lines (multidrop IRQs) can be used as interrupt lines of 5 priorities, or for any other one-to-many signaling.
- a star of single-ended presence detection signals and a service I2C bus (shared among all the slots)
- distribution of two auxiliary voltages to all Peripheral Slots.