17 Feb 2020
1. Power Backplane:
- change 16-pin IDC connector to the SAMTEC EJH-108-02-F-D-SM
- rename layers
- new STEP model to Mikolaj
- commit the design
- DONE!!
send PI report
2. Crate Front Panel:
- change 6-pin pcb-mount connector to 10-pin panel mount IDC connector
- new STEP model to Mikolaj
- commit the design
3. Main Backplane:
- change the 2x 16-pin IDC connectors to the SAMTEC EJH-108-02-F-D-SM
- commit the design
- new STEP model to Mikolaj (Eva will do it once the design is committed)
- send SI report for all high-speed-links including 5Gbps receiver's eye diagram
- DONE!!
send PI report - DONE!!
send SI report for the 3 longest low-speed-links per slot; done at 155MHz; standard LVDS transceiver and receiver used for the modelling
7 Feb 2020
Priorities:
-
Power Backplane:
- PCB modifications to include the new connector, match the position to the Schroff, correct layers naming and add the current sharing jumper ---> today you rename and upload; change IDC connector
- PI for 400W on the 12V and 15W on the 5V, including current densities/temperature distribution and drafting of the report taking into account the comments from below (30 Jan 2020 phonecall).The PI also to explain the selection of the copper thickness. ---> report ready; to be sent today
- step file to Mikolaj to test with Elma and Schroff Power Supplies ---> new step file to be sent
- git commit last design and report ---> to be done today
-
Crate Front Panel:
- PCB design, selecting panel-mount IDC connectors and panel-mount BNC; note that both the rocker switch and the BNC should be interrupting the AC of both power supplies ---> done; 6-pin connector is pcb-mount
- step file to Mikolaj ---> to be sent to Mikolaj
- git commit the design ---> to be done tomorrow
-
Main Backplane:
- PCB modifications for the new IDC connectors ---> change IDC connector
- step file to Mikolaj ---> Eva will do it
- PI including current densities/temperature distribution and report similar to the one for the Power Backplane ---> Done; polygons optimized; report to be sent today/tomorrow
- SI for the 3 longest low-speed-links per slot ---> Done; at 155MHz; standard LVDS transeiver and receiver
- SI for all high-speed-links including 5Gbps receiver's eye diagram ---> Eye parameter receiver not found; GK recommended JSD204 standard; to be discussed tomorrow.
- git commit last design and report
30 Jan 2020
Power backplane PI review:
- Simulate for 400W power supply
- Add thermal distribution/current densities simulations
- Simulate with 35um top layer and check if the increase to 70um is necessary
- Fig1,2: power provided by J1, not the power bag
- Fig1,2: add next to the figures the relevant pcb layout
- Tables: add next to the tables the relevant pcb layout items
- Add a conclusion, for example "simulated drop < 50mV limit"
- Clarify what are the DCPort locations of table 2 and if the double current of row 2 is an issue
- Discussion with GK on AC dynamic loading simulation that would include both backplanes and the cabling between them; note though that hot plugging/unplugging is not really expected on DI/OT crates, however changes may occur on the consumption needs of a borad.
Power Backplane sch:
- Correction of the layers naming
- Addition of the current sharing jumper
28 Jan 2020
-
ACTION A0: Michal to request full availability for DI/OT for the coming 2 weeks so as to boost the end of the project.Done; Michal available for the next 2 weeks. If needed we could also contact Anna for this request. Michal will check with Anna and inform us tomorrow, Wed 29. - ACTION A1: Michal to discuss with K. Kasprowicz on proposed front panel connectors
- ACTION A2: Michal to draw the crate-front-panel pcb
-
ACTION A3: Michal to send us the Main Backplane PI simulations report this week. Please remember the following review comments regarding PI:
- The PI simulations will help identify the thickness of the internal layers for cpci-serial backplane (Copper thickness: currently all internal layers are 18um; should they be increased to 35um? see #3 (closed))
- The power planes of the power backplane will be moved to the outside and with PI the right thickness will be confirmed (if 35um is enough or we would need to move to 70us for example; see #4 (closed))
- For the power supplies please consider >400W on the 12V and >15W on the 5V
- ACTION A4: Michal to continue with Power Backplane PI simulations
- ACTION A5: Michal to send the finalized Power Backplane design
- ACTION A6: Michal to continue with Main Backplane SI simulations; all differential signals to be simulated
- ACTION A7: Michal to send the finalized Main Backplane design
- ACTION A8: Michal to provide STEP models to Mikolaj/Kuba team; they will confirm no mechanical collisions
- ACTION A9: Michal to apply changes from CERN design-office-reviews (see B6-B8) and Mikolaj review (see A7)
ACTION B0: CERN to request to Anna/Greg the full availability of Michal for the coming 2 weeks, if needed-
ACTION B1: Eva to request the following connectors for Altium symbol: EJH-108-02-F-D-SM, 51740-10202402CALF, 51720-10202402AALFDone, waiting DEM - ACTION B2: Eva to ask Orson for the export to KiCad; this will make available the new connectors and the corrections on AMPHENOL_51940-473
- ACTION B3: CERN to review the Hyperlinx simulation reports
- ACTION B4: Eva to produce and test with off-the-shelf power supply a mechanical prototype of the Power Backplane
- ACTION B5: Eva to produce and test with our cpcis boards a mechanical prototype of the Main Backplane
- ACTION B6: Eva to produce and test with our cpcis boards a mechanical prototype of the Crate-front-panel
- ACTION B7: CERN design office to review the Power Backplane and assess conformity to IPC-class 3
- ACTION B8: CERN design office to review the Main Backplane and assess conformity to IPC-class 3
- ACTION B9: CERN design office to review the Crate-Front-Panel and assess conformity to IPC-class 3