2.0.0 - 2020-07-24
=================
https://www.ohwr.org/project/ddr3-sp6-core/tree/v2.0.0

Added
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- Generics to control granularity of Wishbone ports
- Option for active-high reset
- Micron DD3 BFM
- SystemVerilog testbench

Changed
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- Complete rewrite of the Wishbone interface to improve compatibility, performance and code readability

Removed
-------
- Unused file ``rtl/ddr3_ctrl_wb_single.vhd``