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DDR3 controller for Spartan6
Commit 3879a6d3 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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fixed reset polarity

parent 1a129390
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Showing with 11 additions and 9 deletions
hdl/rtl/ddr3_ctrl_wrapper.vhd
View file @ 3879a6d3
......@@ -207,13 +207,15 @@ end entity ddr3_ctrl_wrapper;
architecture rtl of ddr3_ctrl_wrapper is
-- Components generated from Xilinx CoreGen are stored in ddr3_ctrl_wrapper_pkg
signal rst : std_logic;
--==============================================================================
--! Architecure begin
--==============================================================================
begin
rst <= not rst_n_i;
----------------------------------------------------------------------------
-- Selected board/bank check
----------------------------------------------------------------------------
......@@ -251,7 +253,7 @@ begin
)
port map (
c3_sys_clk => clk_i,
c3_sys_rst_i => rst_n_i,
c3_sys_rst_i => rst,
c3_clk0 => open,
c3_rst0 => open,
c3_calib_done => calib_done_o,
......@@ -346,7 +348,7 @@ begin
)
port map (
c3_sys_clk => clk_i,
c3_sys_rst_i => rst_n_i,
c3_sys_rst_i => rst,
c3_clk0 => open,
c3_rst0 => open,
c3_calib_done => calib_done_o,
......@@ -445,7 +447,7 @@ begin
)
port map (
c4_sys_clk => clk_i,
c4_sys_rst_i => rst_n_i,
c4_sys_rst_i => rst,
c4_clk0 => open,
c4_rst0 => open,
c4_calib_done => calib_done_o,
......@@ -540,7 +542,7 @@ begin
)
port map (
c4_sys_clk => clk_i,
c4_sys_rst_i => rst_n_i,
c4_sys_rst_i => rst,
c4_clk0 => open,
c4_rst0 => open,
c4_calib_done => calib_done_o,
......@@ -635,7 +637,7 @@ begin
)
port map (
c5_sys_clk => clk_i,
c5_sys_rst_i => rst_n_i,
c5_sys_rst_i => rst,
c5_clk0 => open,
c5_rst0 => open,
c5_calib_done => calib_done_o,
......@@ -730,7 +732,7 @@ begin
)
port map (
c5_sys_clk => clk_i,
c5_sys_rst_i => rst_n_i,
c5_sys_rst_i => rst,
c5_clk0 => open,
c5_rst0 => open,
c5_calib_done => calib_done_o,
......@@ -829,7 +831,7 @@ begin
)
port map (
c1_sys_clk => clk_i,
c1_sys_rst_i => rst_n_i,
c1_sys_rst_i => rst,
c1_clk0 => open,
c1_rst0 => open,
c1_calib_done => calib_done_o,
......@@ -924,7 +926,7 @@ begin
)
port map (
c1_sys_clk => clk_i,
c1_sys_rst_i => rst_n_i,
c1_sys_rst_i => rst,
c1_clk0 => open,
c1_rst0 => open,
c1_calib_done => calib_done_o,
......
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