Skip to content
GitLab
Explore
Sign in
Projects
DDR3 controller for Spartan6
Repository
ddr3-sp6-core
..
rtl
memc1_infrastructure.vhd
Find file
Blame
History
Permalink
Bypass IBUFG in generated cores to avoid translation errors.
· 59af43bc
mcattin
authored
Jul 16, 2012
git-svn-id:
http://svn.ohwr.org/ddr3-sp6-core/trunk@106
739e5516-d4a2-47df-ba96-5610c1fa693f
59af43bc