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DDR3 controller for Spartan6
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ddr3-sp6-core
hdl
svec
ip_cores
ddr3_ctrl_svec_bank5_32b_32b
example_design
mig.prj
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Change RZQ pin for SVEC bank5 DDR controller from L25 (V0) to G25 (V1 or higher).
· 0ac0a66d
mcattin
authored
Oct 24, 2012
git-svn-id:
http://svn.ohwr.org/ddr3-sp6-core/trunk@109
739e5516-d4a2-47df-ba96-5610c1fa693f
0ac0a66d