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Compact Universal Timing Endpoint Based on White Rabbit with Dual Ports Cute-WR-DP
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Compact Universal Timing Endpoint Based on White Rabbit with Dual Ports Cute-WR-DP
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b3ef6fda4368ee6c07a6acbce7904e87f686cdb0
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cute-wr-dp
schematics
8-FPGA_Power.SchDoc
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Rebuild as lacking of a main clock
· 989f847a
hongming
authored
Mar 22, 2016
989f847a
8-FPGA_Power.SchDoc
513 KB
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