... | ... | @@ -48,16 +48,18 @@ LabVIEW is for example: |
|
|
CRIO-WR is originally derived from and keeps maximum firmware compatibly
|
|
|
with the established boards
|
|
|
[SPEC](https://www.ohwr.org/project/spec/wiki) and
|
|
|
[CUTE-WR](https://www.ohwr.org/project/cute-wr/wiki). CRIO-WR is based
|
|
|
on a FPGA with WR PTP Core plus required hardware to implement a
|
|
|
standalone WR node.
|
|
|
|
|
|
The CompactRIO functionality is ensured by a dedicated power supply with
|
|
|
sleep-mode, a separate EEPROM, an SPI plus some glue logic in the FPGA's
|
|
|
CRIO User Core. A connector at the front panel provides 10 user I/O
|
|
|
signals (protected by TVS), connected directly to the FPGA (programmable
|
|
|
as input/output, LVDS/CMOS, SERDES
|
|
|
etc.)
|
|
|
[CUTE-WR](https://www.ohwr.org/project/cute-wr/wiki).
|
|
|
|
|
|
CRIO-WR is based on a FPGA with WR PTP Core plus required hardware to
|
|
|
implement a standalone WR node.
|
|
|
|
|
|
CompactRIO functionality is ensured by a dedicated power supply with
|
|
|
sleep-mode, a separate EEPROM and an SPI plus some glue logic in the
|
|
|
FPGA's CRIO User Core. A connector at the front panel provides up to 10
|
|
|
user I/O signals (5 x LVDS) protected by TVS, programmable as input or
|
|
|
output, with or without SERDES. The 4 LEDs at the front panel may be
|
|
|
used as status
|
|
|
indicators.
|
|
|
|
|
|
![](/uploads/53e483d47e3d91b35f5ae1b607fcaa3b/crio-wr_1_00_block_diagram.png)
|
|
|
|
... | ... | |