... | ... | @@ -15,27 +15,30 @@ see below). |
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<td><img src="/uploads/170c558f309f3851cad3e6395a2dd028/crio-wr_1_00_module_prototype_small.jpg" alt="" /></td>
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</tr>
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<tr class="even">
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<td>CRIO-WR 1.0 production board</td>
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<td>CRIO-WR v1.0 production board</td>
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<td>CRIO-WR module prototype</td>
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</tr>
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</tbody>
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</table>
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-----
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## Block Diagram
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![](/uploads/53e483d47e3d91b35f5ae1b607fcaa3b/crio-wr_1_00_block_diagram.png)
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CRIO-WR is originally derived from and keeps firmware compatibly with
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the [SPEC](https://www.ohwr.org/project/spec/wiki) /
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[CUTE-WR](https://www.ohwr.org/project/cute-wr/wiki) boards. The
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connector at the front panel provides 10 user I/O, connected directly to
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the FPGA (i.e. programmable as input / output, LVDS / CMOS, SERDES
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etc.). The module is connected over SPI to the CompactRIO
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the [SPEC (SPEC)](https://www.ohwr.org/project/spec/wiki) / [CUTE-WR
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(CUTE-WR)](https://www.ohwr.org/project/cute-wr/wiki) boards. The
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connector at the front panel provides 10 user I/O signals, connected
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directly to the FPGA (i.e. programmable as input/output, LVDS/CMOS,
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SERDES etc.). The module is connected over SPI to the CompactRIO
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backplane/chassis/controller. The functionality in Labview is for
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example reading the status of WR-link, validity of WR-timecode and
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externally triggered WR-timestamps.
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example:
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- Read status of WR-link
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- Read validity of WR-timecode
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- Read externally triggered WR-timestamps
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- Generate output pulses based on
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WR-timecode
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![](/uploads/53e483d47e3d91b35f5ae1b607fcaa3b/crio-wr_1_00_block_diagram.png)
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-----
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... | ... | |