hdl: Added logic for thermometer test

c9d6d24b · Theodor-Adrian Stana · 99466d54 · c9d6d24b
Commit c9d6d24b authored Oct 31, 2014 by Theodor-Adrian Stana
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pts.vhd hdl/top/pts.vhd +45 -0

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--- a/hdl/top/pts.vhd
+++ b/hdl/top/pts.vhd
@@ -494,6 +494,11 @@ architecture arch of pts is
  signal rtm_lines           : std_logic_vector(5 downto 0);
  signal switches            : std_logic_vector(7 downto 0);

+  -- one-wire master signals
+  signal owr_pwren           : std_logic_vector(0 downto 0);
+  signal owr_en              : std_logic_vector(0 downto 0);
+  signal owr_in              : std_logic_vector(0 downto 0);
+
  -- TTL pulse test signals
  signal ttl_pulse_en        : std_logic;
  signal ttl_trigs_a         : std_logic_vector(9 downto 0);
@@ -720,6 +725,46 @@ begin
    end if;
  end process p_rst_fr_reg;

+  --============================================================================
+  -- Thermometer test logic
+  --============================================================================
+  -- The one-wire master component is used to control the on-board DS18B20
+  -- thermometer
+  cmp_onewire_master : wb_onewire_master
+    generic map
+    (
+      g_interface_mode      => CLASSIC,
+      g_address_granularity => WORD,
+      g_num_ports           => 1,
+      g_ow_btp_normal       => "5.0",
+      g_ow_btp_overdrive    => "1.0"
+    )
+    port map
+    (
+      clk_sys_i   => clk_20_i,
+      rst_n_i     => rst_20_n,
+
+      wb_cyc_i    => xbar_master_out(c_slv_onewire_mst).cyc,
+      wb_sel_i    => xbar_master_out(c_slv_onewire_mst).sel,
+      wb_stb_i    => xbar_master_out(c_slv_onewire_mst).stb,
+      wb_we_i     => xbar_master_out(c_slv_onewire_mst).we,
+      wb_adr_i    => xbar_master_out(c_slv_onewire_mst).adr(4 downto 2),
+      wb_dat_i    => xbar_master_out(c_slv_onewire_mst).dat,
+      wb_dat_o    => xbar_master_in(c_slv_onewire_mst).dat,
+      wb_ack_o    => xbar_master_in(c_slv_onewire_mst).ack,
+      wb_int_o    => open,
+      wb_stall_o  => xbar_master_in(c_slv_onewire_mst).stall,
+
+      owr_pwren_o => owr_pwren,
+      owr_en_o    => owr_en,
+      owr_i       => owr_in
+    );
+
+  -- Generate tri-state buffer for thermometer
+  thermometer_b <= '0' when (owr_en(0) = '1') else
+                   'Z';
+  owr_in(0)     <= thermometer_b;
+
  --============================================================================
  -- TTL pulse test logic
  --============================================================================