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Conv TTL RS485 - Testing
Commit 99466d54 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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hdl: Added reset unlock bit

parent 6412605b
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hdl/modules/pts_regs.vhd
View file @ 99466d54
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : pts_regs.vhd
-- Author : auto-generated by wbgen2 from pts_regs.wb
-- Created : Thu Oct 30 17:38:05 2014
-- Created : Fri Oct 31 17:12:29 2014
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pts_regs.wb
......@@ -37,12 +37,16 @@ entity pts_regs is
pts_csr_stat_led_en_o : out std_logic;
-- Port for BIT field: 'TTL pulse enable' in reg: 'CSR'
pts_csr_ttl_en_o : out std_logic;
-- Port for BIT field: 'Blocking pulse enable' in reg: 'CSR'
pts_csr_blo_en_o : out std_logic;
-- Port for BIT field: 'Blocking LED control' in reg: 'CSR'
pts_csr_blo_led_o : out std_logic;
-- Port for BIT field: 'reset' in reg: 'CSR'
-- Port for BIT field: 'Rear pulse enable' in reg: 'CSR'
pts_csr_rear_en_o : out std_logic;
-- Ports for BIT field: 'Reset unlock bit' in reg: 'CSR'
pts_csr_rst_unlock_o : out std_logic;
pts_csr_rst_unlock_i : in std_logic;
pts_csr_rst_unlock_load_o : out std_logic;
-- Ports for BIT field: 'Reset bit' in reg: 'CSR'
pts_csr_rst_o : out std_logic;
pts_csr_rst_i : in std_logic;
pts_csr_rst_load_o : out std_logic;
-- Port for std_logic_vector field: 'switches' in reg: 'CSR'
pts_csr_switch_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'RTM' in reg: 'CSR'
......@@ -64,9 +68,7 @@ signal pts_csr_front_led_en_int : std_logic ;
signal pts_csr_rear_led_en_int : std_logic ;
signal pts_csr_stat_led_en_int : std_logic ;
signal pts_csr_ttl_en_int : std_logic ;
signal pts_csr_blo_en_int : std_logic ;
signal pts_csr_blo_led_int : std_logic ;
signal pts_csr_rst_int : std_logic ;
signal pts_csr_rear_en_int : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
......@@ -98,9 +100,9 @@ begin
pts_csr_rear_led_en_int <= '0';
pts_csr_stat_led_en_int <= '0';
pts_csr_ttl_en_int <= '0';
pts_csr_blo_en_int <= '0';
pts_csr_blo_led_int <= '0';
pts_csr_rst_int <= '0';
pts_csr_rear_en_int <= '0';
pts_csr_rst_unlock_load_o <= '0';
pts_csr_rst_load_o <= '0';
pts_csr_i2c_err_load_o <= '0';
pts_csr_i2c_wdto_load_o <= '0';
elsif rising_edge(clk_sys_i) then
......@@ -109,10 +111,14 @@ begin
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
pts_csr_rst_unlock_load_o <= '0';
pts_csr_rst_load_o <= '0';
pts_csr_i2c_err_load_o <= '0';
pts_csr_i2c_wdto_load_o <= '0';
ack_in_progress <= '0';
else
pts_csr_rst_unlock_load_o <= '0';
pts_csr_rst_load_o <= '0';
pts_csr_i2c_err_load_o <= '0';
pts_csr_i2c_wdto_load_o <= '0';
end if;
......@@ -131,9 +137,9 @@ begin
pts_csr_rear_led_en_int <= wrdata_reg(1);
pts_csr_stat_led_en_int <= wrdata_reg(2);
pts_csr_ttl_en_int <= wrdata_reg(3);
pts_csr_blo_en_int <= wrdata_reg(4);
pts_csr_blo_led_int <= wrdata_reg(5);
pts_csr_rst_int <= wrdata_reg(15);
pts_csr_rear_en_int <= wrdata_reg(4);
pts_csr_rst_unlock_load_o <= '1';
pts_csr_rst_load_o <= '1';
pts_csr_i2c_err_load_o <= '1';
pts_csr_i2c_wdto_load_o <= '1';
end if;
......@@ -141,13 +147,14 @@ begin
rddata_reg(1) <= pts_csr_rear_led_en_int;
rddata_reg(2) <= pts_csr_stat_led_en_int;
rddata_reg(3) <= pts_csr_ttl_en_int;
rddata_reg(4) <= pts_csr_blo_en_int;
rddata_reg(5) <= pts_csr_blo_led_int;
rddata_reg(15) <= pts_csr_rst_int;
rddata_reg(4) <= pts_csr_rear_en_int;
rddata_reg(14) <= pts_csr_rst_unlock_i;
rddata_reg(15) <= pts_csr_rst_i;
rddata_reg(23 downto 16) <= pts_csr_switch_i;
rddata_reg(29 downto 24) <= pts_csr_rtm_i;
rddata_reg(30) <= pts_csr_i2c_err_i;
rddata_reg(31) <= pts_csr_i2c_wdto_i;
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
......@@ -156,7 +163,6 @@ begin
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
......@@ -181,12 +187,12 @@ begin
pts_csr_stat_led_en_o <= pts_csr_stat_led_en_int;
-- TTL pulse enable
pts_csr_ttl_en_o <= pts_csr_ttl_en_int;
-- Blocking pulse enable
pts_csr_blo_en_o <= pts_csr_blo_en_int;
-- Blocking LED control
pts_csr_blo_led_o <= pts_csr_blo_led_int;
-- reset
pts_csr_rst_o <= pts_csr_rst_int;
-- Rear pulse enable
pts_csr_rear_en_o <= pts_csr_rear_en_int;
-- Reset unlock bit
pts_csr_rst_unlock_o <= wrdata_reg(14);
-- Reset bit
pts_csr_rst_o <= wrdata_reg(15);
-- switches
-- RTM
-- I2C communication error
......
hdl/modules/pts_regs.wb
View file @ 99466d54
......@@ -28,6 +28,7 @@ peripheral {
field {
name = "Front pulse LED enable";
prefix = "front_led_en";
description = "1 -- Enable front panel LED sequencing \ 0 -- No effect";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
......@@ -36,6 +37,7 @@ peripheral {
field {
name = "Rear pulse LED enable";
prefix = "rear_led_en";
description = "1 -- Enable rear panel LED sequencing \ 0 -- No effect";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
......@@ -44,6 +46,7 @@ peripheral {
field {
name = "Status LED enable";
prefix = "stat_led_en";
description = "1 -- Enable front panel bicolor LED sequencing \ 0 -- No effect";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
......@@ -52,34 +55,39 @@ peripheral {
field {
name = "TTL pulse enable";
prefix = "ttl_en";
description = "1 -- Enable pulse generation from CH1 \ 0 -- No effect";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Blocking pulse enable";
prefix = "blo_en";
name = "Rear pulse enable";
prefix = "rear_en";
description = "1 -- Enable rear pulse generation \ 0 -- No effect";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Blocking LED control";
prefix = "blo_led";
name = "Reset unlock bit";
description = "1 -- Reset bit unlocked \ 0 -- Reset bit locked";
prefix = "rst_unlock";
type = BIT;
align = 14;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
load = LOAD_EXT;
};
field {
name = "reset";
name = "Reset bit";
description = "1 -- initiate logic reset \ 0 -- no reset";
prefix = "rst";
type = BIT;
align = 15;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
......
hdl/top/pts.vhd
View file @ 99466d54
......@@ -256,12 +256,16 @@ architecture arch of pts is
pts_csr_stat_led_en_o : out std_logic;
-- Port for BIT field: 'TTL pulse enable' in reg: 'CSR'
pts_csr_ttl_en_o : out std_logic;
-- Port for BIT field: 'Blocking pulse enable' in reg: 'CSR'
pts_csr_blo_en_o : out std_logic;
-- Port for BIT field: 'Blocking LED control' in reg: 'CSR'
pts_csr_blo_led_o : out std_logic;
-- Port for BIT field: 'reset' in reg: 'CSR'
-- Port for BIT field: 'Rear pulse enable' in reg: 'CSR'
pts_csr_rear_en_o : out std_logic;
-- Ports for BIT field: 'Reset unlock bit' in reg: 'CSR'
pts_csr_rst_unlock_o : out std_logic;
pts_csr_rst_unlock_i : in std_logic;
pts_csr_rst_unlock_load_o : out std_logic;
-- Ports for BIT field: 'Reset bit' in reg: 'CSR'
pts_csr_rst_o : out std_logic;
pts_csr_rst_i : in std_logic;
pts_csr_rst_load_o : out std_logic;
-- Port for std_logic_vector field: 'switches' in reg: 'CSR'
pts_csr_switch_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'RTM' in reg: 'CSR'
......@@ -448,7 +452,6 @@ architecture arch of pts is
-- Reset signals
signal rst_20_n : std_logic;
signal rst_125_n : std_logic;
signal rst_fr_reg : std_logic;
signal rst_ext : std_logic;
-- I2C bridge signals
......@@ -476,6 +479,12 @@ architecture arch of pts is
signal bicolor_led_state : std_logic_vector(23 downto 0);
-- Signals to/from PTS regs component
signal rst_unlock_ld : std_logic;
signal rst_unlock_ldval : std_logic;
signal rst_unlock : std_logic;
signal rst_bit_ld : std_logic;
signal rst_bit_ldval : std_logic;
signal rst_bit : std_logic;
signal i2c_wdto_bit : std_logic;
signal i2c_wdto_bit_rst : std_logic;
signal i2c_wdto_bit_rst_ld : std_logic;
......@@ -511,7 +520,7 @@ begin
-- Internal reset generation
--============================================================================
-- External reset input to reset generator
rst_ext <= rst_fr_reg or (not vme_sysreset_n_i);
rst_ext <= rst_bit or (not vme_sysreset_n_i);
-- Configure reset generator for 100ms reset
cmp_reset_gen : conv_reset_gen
......@@ -659,23 +668,58 @@ begin
pts_bidr_i => c_board_id,
-- PTS control register
pts_csr_front_led_en_o => pulse_led_en,
pts_csr_rear_led_en_o => open,
pts_csr_stat_led_en_o => stat_led_en,
pts_csr_ttl_en_o => ttl_pulse_en,
pts_csr_blo_en_o => open,
pts_csr_blo_led_o => open,
pts_csr_rst_o => rst_fr_reg,
pts_csr_switch_i => switches,
pts_csr_rtm_i => rtm_lines,
pts_csr_i2c_err_o => i2c_err_bit_rst,
pts_csr_i2c_err_i => i2c_err_bit,
pts_csr_i2c_err_load_o => i2c_err_bit_rst_ld,
pts_csr_i2c_wdto_o => i2c_wdto_bit_rst,
pts_csr_i2c_wdto_i => i2c_wdto_bit,
pts_csr_i2c_wdto_load_o => i2c_wdto_bit_rst_ld
pts_csr_front_led_en_o => pulse_led_en,
pts_csr_rear_led_en_o => open,
pts_csr_stat_led_en_o => stat_led_en,
pts_csr_ttl_en_o => ttl_pulse_en,
pts_csr_rear_en_o => open,
pts_csr_rst_unlock_o => rst_unlock_ldval,
pts_csr_rst_unlock_i => rst_unlock,
pts_csr_rst_unlock_load_o => rst_unlock_ld,
pts_csr_rst_o => rst_bit_ldval,
pts_csr_rst_i => rst_bit,
pts_csr_rst_load_o => rst_bit_ld,
pts_csr_switch_i => switches,
pts_csr_rtm_i => rtm_lines,
pts_csr_i2c_err_o => i2c_err_bit_rst,
pts_csr_i2c_err_i => i2c_err_bit,
pts_csr_i2c_err_load_o => i2c_err_bit_rst_ld,
pts_csr_i2c_wdto_o => i2c_wdto_bit_rst,
pts_csr_i2c_wdto_i => i2c_wdto_bit,
pts_csr_i2c_wdto_load_o => i2c_wdto_bit_rst_ld
);
-- Implement the RST_UNLOCK bit
p_rst_unlock : process (clk_20_i)
begin
if rising_edge(clk_20_i) then
if (rst_20_n = '0') then
rst_unlock <= '0';
elsif (rst_unlock_ld = '1') then
if (rst_unlock_ldval = '1') then
rst_unlock <= '1';
else
rst_unlock <= '0';
end if;
end if;
end if;
end process p_rst_unlock;
-- Implement the reset bit register
-- The register can only be set when the RST_UNLOCK bit is '1'.
p_rst_fr_reg : process (clk_20_i)
begin
if rising_edge(clk_20_i) then
if (rst_20_n = '0') then
rst_bit <= '0';
elsif (rst_bit_ld = '1') and (rst_bit_ldval = '1') and (rst_unlock = '1') then
rst_bit <= '1';
else
rst_bit <= '0';
end if;
end if;
end process p_rst_fr_reg;
--============================================================================
-- TTL pulse test logic
--============================================================================
......
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