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Conv TTL RS485 - Testing
Commit 92e725dc authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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hdl: Moved LED bits to first position in pts_regs CSR

parent 2507695c
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hdl/modules/pts_regs.vhd
View file @ 92e725dc
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : pts_regs.vhd -- File : pts_regs.vhd
-- Author : auto-generated by wbgen2 from pts_regs.wb -- Author : auto-generated by wbgen2 from pts_regs.wb
-- Created : Thu Oct 30 17:06:40 2014 -- Created : Thu Oct 30 17:38:05 2014
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pts_regs.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pts_regs.wb
...@@ -29,16 +29,18 @@ entity pts_regs is ...@@ -29,16 +29,18 @@ entity pts_regs is
wb_stall_o : out std_logic; wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'ID register bits' in reg: 'BIDR' -- Port for std_logic_vector field: 'ID register bits' in reg: 'BIDR'
pts_bidr_i : in std_logic_vector(31 downto 0); pts_bidr_i : in std_logic_vector(31 downto 0);
-- Port for BIT field: 'Front pulse LED enable' in reg: 'CSR'
pts_csr_front_led_en_o : out std_logic;
-- Port for BIT field: 'Rear pulse LED enable' in reg: 'CSR'
pts_csr_rear_led_en_o : out std_logic;
-- Port for BIT field: 'Status LED enable' in reg: 'CSR'
pts_csr_stat_led_en_o : out std_logic;
-- Port for BIT field: 'TTL pulse enable' in reg: 'CSR' -- Port for BIT field: 'TTL pulse enable' in reg: 'CSR'
pts_csr_ttl_en_o : out std_logic; pts_csr_ttl_en_o : out std_logic;
-- Port for BIT field: 'Blocking pulse enable' in reg: 'CSR' -- Port for BIT field: 'Blocking pulse enable' in reg: 'CSR'
pts_csr_blo_en_o : out std_logic; pts_csr_blo_en_o : out std_logic;
-- Port for BIT field: 'Blocking LED control' in reg: 'CSR' -- Port for BIT field: 'Blocking LED control' in reg: 'CSR'
pts_csr_blo_led_o : out std_logic; pts_csr_blo_led_o : out std_logic;
-- Port for BIT field: 'pulse LED enable' in reg: 'CSR'
pts_csr_pulse_led_en_o : out std_logic;
-- Port for BIT field: 'status LED enable' in reg: 'CSR'
pts_csr_stat_led_en_o : out std_logic;
-- Port for BIT field: 'reset' in reg: 'CSR' -- Port for BIT field: 'reset' in reg: 'CSR'
pts_csr_rst_o : out std_logic; pts_csr_rst_o : out std_logic;
-- Port for std_logic_vector field: 'switches' in reg: 'CSR' -- Port for std_logic_vector field: 'switches' in reg: 'CSR'
...@@ -58,11 +60,12 @@ end pts_regs; ...@@ -58,11 +60,12 @@ end pts_regs;
architecture syn of pts_regs is architecture syn of pts_regs is
signal pts_csr_front_led_en_int : std_logic ;
signal pts_csr_rear_led_en_int : std_logic ;
signal pts_csr_stat_led_en_int : std_logic ;
signal pts_csr_ttl_en_int : std_logic ; signal pts_csr_ttl_en_int : std_logic ;
signal pts_csr_blo_en_int : std_logic ; signal pts_csr_blo_en_int : std_logic ;
signal pts_csr_blo_led_int : std_logic ; signal pts_csr_blo_led_int : std_logic ;
signal pts_csr_pulse_led_en_int : std_logic ;
signal pts_csr_stat_led_en_int : std_logic ;
signal pts_csr_rst_int : std_logic ; signal pts_csr_rst_int : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0); signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0); signal rddata_reg : std_logic_vector(31 downto 0);
...@@ -91,11 +94,12 @@ begin ...@@ -91,11 +94,12 @@ begin
ack_sreg <= "0000000000"; ack_sreg <= "0000000000";
ack_in_progress <= '0'; ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000"; rddata_reg <= "00000000000000000000000000000000";
pts_csr_front_led_en_int <= '0';
pts_csr_rear_led_en_int <= '0';
pts_csr_stat_led_en_int <= '0';
pts_csr_ttl_en_int <= '0'; pts_csr_ttl_en_int <= '0';
pts_csr_blo_en_int <= '0'; pts_csr_blo_en_int <= '0';
pts_csr_blo_led_int <= '0'; pts_csr_blo_led_int <= '0';
pts_csr_pulse_led_en_int <= '0';
pts_csr_stat_led_en_int <= '0';
pts_csr_rst_int <= '0'; pts_csr_rst_int <= '0';
pts_csr_i2c_err_load_o <= '0'; pts_csr_i2c_err_load_o <= '0';
pts_csr_i2c_wdto_load_o <= '0'; pts_csr_i2c_wdto_load_o <= '0';
...@@ -123,26 +127,27 @@ begin ...@@ -123,26 +127,27 @@ begin
ack_in_progress <= '1'; ack_in_progress <= '1';
when '1' => when '1' =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
pts_csr_ttl_en_int <= wrdata_reg(0); pts_csr_front_led_en_int <= wrdata_reg(0);
pts_csr_blo_en_int <= wrdata_reg(1); pts_csr_rear_led_en_int <= wrdata_reg(1);
pts_csr_blo_led_int <= wrdata_reg(2); pts_csr_stat_led_en_int <= wrdata_reg(2);
pts_csr_pulse_led_en_int <= wrdata_reg(3); pts_csr_ttl_en_int <= wrdata_reg(3);
pts_csr_stat_led_en_int <= wrdata_reg(4); pts_csr_blo_en_int <= wrdata_reg(4);
pts_csr_blo_led_int <= wrdata_reg(5);
pts_csr_rst_int <= wrdata_reg(15); pts_csr_rst_int <= wrdata_reg(15);
pts_csr_i2c_err_load_o <= '1'; pts_csr_i2c_err_load_o <= '1';
pts_csr_i2c_wdto_load_o <= '1'; pts_csr_i2c_wdto_load_o <= '1';
end if; end if;
rddata_reg(0) <= pts_csr_ttl_en_int; rddata_reg(0) <= pts_csr_front_led_en_int;
rddata_reg(1) <= pts_csr_blo_en_int; rddata_reg(1) <= pts_csr_rear_led_en_int;
rddata_reg(2) <= pts_csr_blo_led_int; rddata_reg(2) <= pts_csr_stat_led_en_int;
rddata_reg(3) <= pts_csr_pulse_led_en_int; rddata_reg(3) <= pts_csr_ttl_en_int;
rddata_reg(4) <= pts_csr_stat_led_en_int; rddata_reg(4) <= pts_csr_blo_en_int;
rddata_reg(5) <= pts_csr_blo_led_int;
rddata_reg(15) <= pts_csr_rst_int; rddata_reg(15) <= pts_csr_rst_int;
rddata_reg(23 downto 16) <= pts_csr_switch_i; rddata_reg(23 downto 16) <= pts_csr_switch_i;
rddata_reg(29 downto 24) <= pts_csr_rtm_i; rddata_reg(29 downto 24) <= pts_csr_rtm_i;
rddata_reg(30) <= pts_csr_i2c_err_i; rddata_reg(30) <= pts_csr_i2c_err_i;
rddata_reg(31) <= pts_csr_i2c_wdto_i; rddata_reg(31) <= pts_csr_i2c_wdto_i;
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X'; rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X'; rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X'; rddata_reg(8) <= 'X';
...@@ -168,16 +173,18 @@ begin ...@@ -168,16 +173,18 @@ begin
-- Drive the data output bus -- Drive the data output bus
wb_dat_o <= rddata_reg; wb_dat_o <= rddata_reg;
-- ID register bits -- ID register bits
-- Front pulse LED enable
pts_csr_front_led_en_o <= pts_csr_front_led_en_int;
-- Rear pulse LED enable
pts_csr_rear_led_en_o <= pts_csr_rear_led_en_int;
-- Status LED enable
pts_csr_stat_led_en_o <= pts_csr_stat_led_en_int;
-- TTL pulse enable -- TTL pulse enable
pts_csr_ttl_en_o <= pts_csr_ttl_en_int; pts_csr_ttl_en_o <= pts_csr_ttl_en_int;
-- Blocking pulse enable -- Blocking pulse enable
pts_csr_blo_en_o <= pts_csr_blo_en_int; pts_csr_blo_en_o <= pts_csr_blo_en_int;
-- Blocking LED control -- Blocking LED control
pts_csr_blo_led_o <= pts_csr_blo_led_int; pts_csr_blo_led_o <= pts_csr_blo_led_int;
-- pulse LED enable
pts_csr_pulse_led_en_o <= pts_csr_pulse_led_en_int;
-- status LED enable
pts_csr_stat_led_en_o <= pts_csr_stat_led_en_int;
-- reset -- reset
pts_csr_rst_o <= pts_csr_rst_int; pts_csr_rst_o <= pts_csr_rst_int;
-- switches -- switches
......
hdl/modules/pts_regs.wb
View file @ 92e725dc
...@@ -26,40 +26,48 @@ peripheral { ...@@ -26,40 +26,48 @@ peripheral {
prefix = "csr"; prefix = "csr";
field { field {
name = "TTL pulse enable"; name = "Front pulse LED enable";
prefix = "ttl_en"; prefix = "front_led_en";
type = BIT; type = BIT;
access_bus = READ_WRITE; access_bus = READ_WRITE;
access_dev = READ_ONLY; access_dev = READ_ONLY;
}; };
field { field {
name = "Blocking pulse enable"; name = "Rear pulse LED enable";
prefix = "blo_en"; prefix = "rear_led_en";
type = BIT; type = BIT;
access_bus = READ_WRITE; access_bus = READ_WRITE;
access_dev = READ_ONLY; access_dev = READ_ONLY;
}; };
field { field {
name = "Blocking LED control"; name = "Status LED enable";
prefix = "blo_led"; prefix = "stat_led_en";
type = BIT; type = BIT;
access_bus = READ_WRITE; access_bus = READ_WRITE;
access_dev = READ_ONLY; access_dev = READ_ONLY;
}; };
field { field {
name = "pulse LED enable"; name = "TTL pulse enable";
prefix = "pulse_led_en"; prefix = "ttl_en";
type = BIT; type = BIT;
access_bus = READ_WRITE; access_bus = READ_WRITE;
access_dev = READ_ONLY; access_dev = READ_ONLY;
}; };
field { field {
name = "status LED enable"; name = "Blocking pulse enable";
prefix = "stat_led_en"; prefix = "blo_en";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Blocking LED control";
prefix = "blo_led";
type = BIT; type = BIT;
access_bus = READ_WRITE; access_bus = READ_WRITE;
access_dev = READ_ONLY; access_dev = READ_ONLY;
......
hdl/top/pts.vhd
View file @ 92e725dc
...@@ -245,21 +245,23 @@ architecture arch of pts is ...@@ -245,21 +245,23 @@ architecture arch of pts is
wb_stall_o : out std_logic; wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'ID register bits' in reg: 'BIDR' -- Port for std_logic_vector field: 'ID register bits' in reg: 'BIDR'
pts_bidr_i : in std_logic_vector(31 downto 0); pts_bidr_i : in std_logic_vector(31 downto 0);
-- Port for BIT field: 'TTL pulse enable' in reg: 'control and status register' -- Port for BIT field: 'Front pulse LED enable' in reg: 'CSR'
pts_csr_front_led_en_o : out std_logic;
-- Port for BIT field: 'Rear pulse LED enable' in reg: 'CSR'
pts_csr_rear_led_en_o : out std_logic;
-- Port for BIT field: 'Status LED enable' in reg: 'CSR'
pts_csr_stat_led_en_o : out std_logic;
-- Port for BIT field: 'TTL pulse enable' in reg: 'CSR'
pts_csr_ttl_en_o : out std_logic; pts_csr_ttl_en_o : out std_logic;
-- Port for BIT field: 'Blocking pulse enable' in reg: 'control and status register' -- Port for BIT field: 'Blocking pulse enable' in reg: 'CSR'
pts_csr_blo_en_o : out std_logic; pts_csr_blo_en_o : out std_logic;
-- Port for BIT field: 'Blocking LED control' in reg: 'control and status register' -- Port for BIT field: 'Blocking LED control' in reg: 'CSR'
pts_csr_blo_led_o : out std_logic; pts_csr_blo_led_o : out std_logic;
-- Port for BIT field: 'pulse LED enable' in reg: 'control and status register' -- Port for BIT field: 'reset' in reg: 'CSR'
pts_csr_pulse_led_en_o : out std_logic;
-- Port for BIT field: 'status LED enable' in reg: 'control and status register'
pts_csr_stat_led_en_o : out std_logic;
-- Port for BIT field: 'reset' in reg: 'control and status register'
pts_csr_rst_o : out std_logic; pts_csr_rst_o : out std_logic;
-- Port for std_logic_vector field: 'switches' in reg: 'control and status register' -- Port for std_logic_vector field: 'switches' in reg: 'CSR'
pts_csr_switch_i : in std_logic_vector(7 downto 0); pts_csr_switch_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'RTM' in reg: 'control and status register' -- Port for std_logic_vector field: 'RTM' in reg: 'CSR'
pts_csr_rtm_i : in std_logic_vector(5 downto 0); pts_csr_rtm_i : in std_logic_vector(5 downto 0);
-- Ports for BIT field: 'I2C communication error' in reg: 'CSR' -- Ports for BIT field: 'I2C communication error' in reg: 'CSR'
pts_csr_i2c_err_o : out std_logic; pts_csr_i2c_err_o : out std_logic;
...@@ -472,11 +474,12 @@ begin ...@@ -472,11 +474,12 @@ begin
pts_bidr_i => c_board_id, pts_bidr_i => c_board_id,
-- PTS control register -- PTS control register
pts_csr_front_led_en_o => pulse_led_en,
pts_csr_rear_led_en_o => open,
pts_csr_stat_led_en_o => stat_led_en,
pts_csr_ttl_en_o => open, pts_csr_ttl_en_o => open,
pts_csr_blo_en_o => open, pts_csr_blo_en_o => open,
pts_csr_blo_led_o => open, pts_csr_blo_led_o => open,
pts_csr_pulse_led_en_o => pulse_led_en,
pts_csr_stat_led_en_o => stat_led_en,
pts_csr_rst_o => rst_fr_reg, pts_csr_rst_o => rst_fr_reg,
pts_csr_switch_i => switches, pts_csr_switch_i => switches,
pts_csr_rtm_i => rtm_lines, pts_csr_rtm_i => rtm_lines,
......
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