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Conv TTL RS485 - Testing
Commit 2507695c authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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hdl: Front panel LED test now working

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hdl/modules/Manifest.py 0 → 100644
View file @ 2507695c
files = [
"pts_regs.vhd",
"pulse_cnt_wb.vhd",
"incr_counter.vhd",
"clk_info_wb_slave.vhd"
]
hdl/modules/clk_info_wb_slave.vhd 0 → 100644
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hdl/modules/incr_counter.vhd 0 → 100644
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--_________________________________________________________________________________________________
-- |
-- |TDC core| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- incr_counter |
-- |
---------------------------------------------------------------------------------------------------
-- File incr_counter.vhd |
-- |
-- Description Stop counter. Configurable counter_top_i and width. |
-- Current count value and done signal available. |
-- Done signal asserted simultaneous to value = counter_top_i. |
-- Needs a rst_i to restart. |
-- |
-- |
-- Authors Gonzalo Penacoba (Gonzalo.Penacoba@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 04/2012 |
-- Version v0.11 |
-- Depends on |
-- |
---------------- |
-- Last changes |
-- 05/2011 v0.1 GP First version |
-- 04/2012 v0.11 EG Revamping; Comments added, signals renamed |
-- |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
--=================================================================================================
-- Entity declaration for incr_counter
--=================================================================================================
entity incr_counter is
generic
(width : integer := 32); -- default size
port
-- INPUTS
-- Signals from the clk_rst_manager
(clk_i : in std_logic;
rst_i : in std_logic;
-- Signals from any unit
counter_top_i : in std_logic_vector(width-1 downto 0); -- max value to be counted; when reached
-- counter stays at it, until a reset
counter_incr_en_i : in std_logic; -- enables counting
-- OUTPUTS
-- Signals to any unit
counter_o : out std_logic_vector(width-1 downto 0);
counter_is_full_o : out std_logic); -- counter reahed counter_top_i value
end incr_counter;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of incr_counter is
constant zeroes : unsigned(width-1 downto 0) := (others=>'0');
signal counter : unsigned(width-1 downto 0) := (others=>'0'); -- init to avoid sim warnings
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
incr_counting: process (clk_i)
begin
if rising_edge (clk_i) then
if rst_i = '1' then
counter_is_full_o <= '0';
counter <= zeroes;
elsif counter = unsigned (counter_top_i) then
counter_is_full_o <= '1';
counter <= unsigned (counter_top_i);
elsif counter_incr_en_i ='1' then
if counter = unsigned(counter_top_i) - "1" then
counter_is_full_o <= '1';
counter <= counter + "1";
else
counter_is_full_o <= '0';
counter <= counter + "1";
end if;
end if;
end if;
end process;
counter_o <= std_logic_vector(counter);
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
hdl/modules/pts_regs.vhd 0 → 100644
View file @ 2507695c
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for PTS control and status registers
---------------------------------------------------------------------------------------
-- File : pts_regs.vhd
-- Author : auto-generated by wbgen2 from pts_regs.wb
-- Created : Thu Oct 30 17:06:40 2014
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pts_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pts_regs is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(0 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'ID register bits' in reg: 'BIDR'
pts_bidr_i : in std_logic_vector(31 downto 0);
-- Port for BIT field: 'TTL pulse enable' in reg: 'CSR'
pts_csr_ttl_en_o : out std_logic;
-- Port for BIT field: 'Blocking pulse enable' in reg: 'CSR'
pts_csr_blo_en_o : out std_logic;
-- Port for BIT field: 'Blocking LED control' in reg: 'CSR'
pts_csr_blo_led_o : out std_logic;
-- Port for BIT field: 'pulse LED enable' in reg: 'CSR'
pts_csr_pulse_led_en_o : out std_logic;
-- Port for BIT field: 'status LED enable' in reg: 'CSR'
pts_csr_stat_led_en_o : out std_logic;
-- Port for BIT field: 'reset' in reg: 'CSR'
pts_csr_rst_o : out std_logic;
-- Port for std_logic_vector field: 'switches' in reg: 'CSR'
pts_csr_switch_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'RTM' in reg: 'CSR'
pts_csr_rtm_i : in std_logic_vector(5 downto 0);
-- Ports for BIT field: 'I2C communication error' in reg: 'CSR'
pts_csr_i2c_err_o : out std_logic;
pts_csr_i2c_err_i : in std_logic;
pts_csr_i2c_err_load_o : out std_logic;
-- Ports for BIT field: 'I2C communication watchdog timeout error' in reg: 'CSR'
pts_csr_i2c_wdto_o : out std_logic;
pts_csr_i2c_wdto_i : in std_logic;
pts_csr_i2c_wdto_load_o : out std_logic
);
end pts_regs;
architecture syn of pts_regs is
signal pts_csr_ttl_en_int : std_logic ;
signal pts_csr_blo_en_int : std_logic ;
signal pts_csr_blo_led_int : std_logic ;
signal pts_csr_pulse_led_en_int : std_logic ;
signal pts_csr_stat_led_en_int : std_logic ;
signal pts_csr_rst_int : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(0 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
pts_csr_ttl_en_int <= '0';
pts_csr_blo_en_int <= '0';
pts_csr_blo_led_int <= '0';
pts_csr_pulse_led_en_int <= '0';
pts_csr_stat_led_en_int <= '0';
pts_csr_rst_int <= '0';
pts_csr_i2c_err_load_o <= '0';
pts_csr_i2c_wdto_load_o <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
pts_csr_i2c_err_load_o <= '0';
pts_csr_i2c_wdto_load_o <= '0';
ack_in_progress <= '0';
else
pts_csr_i2c_err_load_o <= '0';
pts_csr_i2c_wdto_load_o <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(0) is
when '0' =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pts_bidr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when '1' =>
if (wb_we_i = '1') then
pts_csr_ttl_en_int <= wrdata_reg(0);
pts_csr_blo_en_int <= wrdata_reg(1);
pts_csr_blo_led_int <= wrdata_reg(2);
pts_csr_pulse_led_en_int <= wrdata_reg(3);
pts_csr_stat_led_en_int <= wrdata_reg(4);
pts_csr_rst_int <= wrdata_reg(15);
pts_csr_i2c_err_load_o <= '1';
pts_csr_i2c_wdto_load_o <= '1';
end if;
rddata_reg(0) <= pts_csr_ttl_en_int;
rddata_reg(1) <= pts_csr_blo_en_int;
rddata_reg(2) <= pts_csr_blo_led_int;
rddata_reg(3) <= pts_csr_pulse_led_en_int;
rddata_reg(4) <= pts_csr_stat_led_en_int;
rddata_reg(15) <= pts_csr_rst_int;
rddata_reg(23 downto 16) <= pts_csr_switch_i;
rddata_reg(29 downto 24) <= pts_csr_rtm_i;
rddata_reg(30) <= pts_csr_i2c_err_i;
rddata_reg(31) <= pts_csr_i2c_wdto_i;
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- ID register bits
-- TTL pulse enable
pts_csr_ttl_en_o <= pts_csr_ttl_en_int;
-- Blocking pulse enable
pts_csr_blo_en_o <= pts_csr_blo_en_int;
-- Blocking LED control
pts_csr_blo_led_o <= pts_csr_blo_led_int;
-- pulse LED enable
pts_csr_pulse_led_en_o <= pts_csr_pulse_led_en_int;
-- status LED enable
pts_csr_stat_led_en_o <= pts_csr_stat_led_en_int;
-- reset
pts_csr_rst_o <= pts_csr_rst_int;
-- switches
-- RTM
-- I2C communication error
pts_csr_i2c_err_o <= wrdata_reg(30);
-- I2C communication watchdog timeout error
pts_csr_i2c_wdto_o <= wrdata_reg(31);
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
hdl/modules/pts_regs.wb 0 → 100644
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peripheral {
name = "PTS control and status registers";
description = "Registers of the PTS firmware";
hdl_entity = "pts_regs";
prefix = "pts";
-- Board ID register
reg {
name = "BIDR";
description = "Board ID Register";
prefix = "bidr";
reset_value = "g_board_id";
field {
name = "ID register bits";
reset_value = "g_board_id";
type = SLV;
size = 32;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
-- Control & Status Register
reg {
name = "CSR";
prefix = "csr";
field {
name = "TTL pulse enable";
prefix = "ttl_en";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Blocking pulse enable";
prefix = "blo_en";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Blocking LED control";
prefix = "blo_led";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "pulse LED enable";
prefix = "pulse_led_en";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "status LED enable";
prefix = "stat_led_en";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "reset";
prefix = "rst";
type = BIT;
align = 15;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "switches";
prefix = "switch";
type = SLV;
align = 16;
size = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "RTM";
prefix = "rtm";
type = SLV;
align = 24;
size = 6;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "I2C communication error";
description = "1 -- attempted to address non-existing address \
0 -- idle \
This bit can be cleared by writing a '1' to it";
prefix = "i2c_err";
type = BIT;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "I2C communication watchdog timeout error";
description = "1 -- timeout occured \
0 -- no timeout \
This bit can be cleared by writing a '1' to it";
prefix = "i2c_wdto";
type = BIT;
size = 1;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
};
};
hdl/modules/pulse_cnt_wb.vhd 0 → 100644
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hdl/modules/pulse_cnt_wb.wb 0 → 100644
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peripheral {
name = "Pulse counter registers";
description = "Registers containing the values for input and output generated pulses";
hdl_entity = "pulse_cnt_wb";
prefix = "pulse_cnt";
reg {
name = "CH1 output";
prefix = "ch1o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH1 input";
prefix = "ch1i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH2 output";
prefix = "ch2o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH2 input";
prefix = "ch2i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH3 output";
prefix = "ch3o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH3 input";
prefix = "ch3i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH4 output";
prefix = "ch4o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH4 input";
prefix = "ch4i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH5 output";
prefix = "ch5o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH5 input";
prefix = "ch5i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH6 output";
prefix = "ch6o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH6 input";
prefix = "ch6i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH7 output";
prefix = "ch7o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH7 input";
prefix = "ch7i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH8 output";
prefix = "ch8o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH8 input";
prefix = "ch8i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH9 output";
prefix = "ch9o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH9 input";
prefix = "ch9i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH10 output";
prefix = "ch10o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH10 input";
prefix = "ch10i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH11 output";
prefix = "ch11o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH11 input";
prefix = "ch11i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH12 output";
prefix = "ch12o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH12 input";
prefix = "ch12i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH13 output";
prefix = "ch13o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH13 input";
prefix = "ch13i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH14 output";
prefix = "ch14o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH14 input";
prefix = "ch14i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH15 output";
prefix = "ch15o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH15 input";
prefix = "ch15i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH16 output";
prefix = "ch16o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH16 input";
prefix = "ch16i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
};
hdl/syn/Makefile 0 → 100644
View file @ 2507695c
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
PROJECT := pts.xise
ISE_CRAP := *.b pts_summary.html *.tcl pts.bld pts.cmd_log *.drc pts.lso *.ncd pts.ngc pts.ngd pts.ngr pts.pad pts.par pts.pcf pts.prj pts.ptwx pts.stx pts.syr pts.twr pts.twx pts.gise pts.unroutes pts.ut pts.xpi pts.xst pts_bitgen.xwbt pts_envsettings.html pts_guide.ncd pts_map.map pts_map.mrp pts_map.ncd pts_map.ngm pts_map.xrpt pts_ngdbuild.xrpt pts_pad.csv pts_pad.txt pts_par.xrpt pts_summary.xml pts_usage.xml pts_xst.xrpt usage_statistics_webtalk.html webtalk.log webtalk_pn.xml run.tcl
#target for performing local synthesis
local:
echo "project open $(PROJECT)" > run.tcl
echo "process run {Generate Programming File} -force rerun_all" >> run.tcl
xtclsh run.tcl
#target for cleaing all intermediate stuff
clean:
rm -f $(ISE_CRAP)
rm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo
#target for cleaning final files
mrproper:
rm -f *.bit *.bin *.mcs
hdl/syn/Manifest.py 0 → 100644
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target = "xilinx"
action = "synthesis"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "pts"
syn_project = "pts.xise"
modules = {
"local" : [
"../top"
]
}
hdl/syn/pts.xise 0 → 100644
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hdl/top/Manifest.py 0 → 100644
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files = [
"pts.ucf",
"pts.vhd"
]
modules = {
"local" : [
"../modules",
"../ip_cores/conv-common-gw"
],
}
hdl/top/pts.ucf 0 → 100644
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hdl/top/pts.vhd 0 → 100644
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