Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
C
Conv TTL RS485 - Testing
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
3
Issues
3
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
Conv TTL RS485 - Testing
Commits
8a67d16a
Commit
8a67d16a
authored
Nov 11, 2014
by
Theodor-Adrian Stana
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
hdl: LEDs also light on pulse output
parent
70750c9a
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
with
97 additions
and
66 deletions
+97
-66
pts.vhd
hdl/top/pts.vhd
+97
-66
No files found.
hdl/top/pts.vhd
View file @
8a67d16a
...
@@ -160,6 +160,7 @@ architecture arch of pts is
...
@@ -160,6 +160,7 @@ architecture arch of pts is
-- Pulse counter register and load value types
-- Pulse counter register and load value types
type
t_pcr
is
array
(
15
downto
0
)
of
unsigned
(
31
downto
0
);
type
t_pcr
is
array
(
15
downto
0
)
of
unsigned
(
31
downto
0
);
type
t_pcr_ldval
is
array
(
15
downto
0
)
of
std_logic_vector
(
31
downto
0
);
type
t_pcr_ldval
is
array
(
15
downto
0
)
of
std_logic_vector
(
31
downto
0
);
type
t_pulse_led_cnt
is
array
(
9
downto
0
)
of
unsigned
(
18
downto
0
);
--============================================================================
--============================================================================
-- Constant declarations
-- Constant declarations
...
@@ -589,7 +590,10 @@ architecture arch of pts is
...
@@ -589,7 +590,10 @@ architecture arch of pts is
signal
pulse_led_en_risedge
:
std_logic
;
signal
pulse_led_en_risedge
:
std_logic
;
signal
stat_led_en_risedge
:
std_logic
;
signal
stat_led_en_risedge
:
std_logic
;
signal
pulse_led_seq
:
std_logic_vector
(
5
downto
0
);
signal
pulse_led_seq
:
std_logic_vector
(
5
downto
0
);
signal
inv_led
:
std_logic_vector
(
3
downto
0
);
signal
inv_led_seq
:
std_logic_vector
(
3
downto
0
);
signal
inv_led_seq
:
std_logic_vector
(
3
downto
0
);
signal
pulse_led
:
std_logic_vector
(
9
downto
0
);
signal
pulse_led_cnt
:
t_pulse_led_cnt
;
signal
bicolor_led_state
:
std_logic_vector
(
23
downto
0
);
signal
bicolor_led_state
:
std_logic_vector
(
23
downto
0
);
-- Signals to/from PTS regs component
-- Signals to/from PTS regs component
...
@@ -1436,17 +1440,17 @@ begin
...
@@ -1436,17 +1440,17 @@ begin
ttl_trigs_a
(
9
downto
6
)
<=
not
inv_n_i
;
ttl_trigs_a
(
9
downto
6
)
<=
not
inv_n_i
;
-- Synchronize these signals in the 20-MHz clock domain
-- Synchronize these signals in the 20-MHz clock domain
gen_ttl_sync_chains
:
for
i
in
0
to
9
generate
gen_ttl_sync_chains
:
for
i
in
0
to
9
generate
cmp_ttl_sync_chain
:
gc_sync_ffs
cmp_ttl_sync_chain
:
gc_sync_ffs
port
map
port
map
(
(
clk_i
=>
clk_20_i
,
clk_i
=>
clk_20_i
,
rst_n_i
=>
rst_20_n
,
rst_n_i
=>
rst_20_n
,
data_i
=>
ttl_trigs_a
(
i
),
data_i
=>
ttl_trigs_a
(
i
),
synced_o
=>
ttl_trigs
(
i
),
synced_o
=>
ttl_trigs
(
i
),
ppulse_o
=>
ttl_trigs_redge_p
(
i
)
ppulse_o
=>
ttl_trigs_redge_p
(
i
)
);
);
end
generate
gen_ttl_sync_chains
;
end
generate
gen_ttl_sync_chains
;
-- Now, generate nine pulse generator blocks connected to the TTL outputs
-- Now, generate nine pulse generator blocks connected to the TTL outputs
-- and with the TTL inputs as triggers.
-- and with the TTL inputs as triggers.
...
@@ -1457,74 +1461,100 @@ begin
...
@@ -1457,74 +1461,100 @@ begin
-- be connected back to the input of CH1.
-- be connected back to the input of CH1.
--
--
-- The pulse generator is configured for fixed-width pulses of 1us.
-- The pulse generator is configured for fixed-width pulses of 1us.
gen_ttl_pulse_gens
:
for
i
in
1
to
9
generate
gen_ttl_pulse_gens
:
for
i
in
1
to
9
generate
cmp_pulse_gens
:
conv_pulse_gen
cmp_pulse_gens
:
conv_pulse_gen
generic
map
generic
map
(
(
g_with_fixed_pwidth
=>
true
,
g_with_fixed_pwidth
=>
true
,
g_pwidth
=>
20
,
g_pwidth
=>
20
,
g_duty_cycle_div
=>
5
g_duty_cycle_div
=>
5
)
)
port
map
port
map
(
(
clk_i
=>
clk_20_i
,
clk_i
=>
clk_20_i
,
rst_n_i
=>
rst_20_n
,
rst_n_i
=>
rst_20_n
,
gf_en_n_i
=>
'1'
,
gf_en_n_i
=>
'1'
,
en_i
=>
ttl_pulse_en
,
en_i
=>
ttl_pulse_en
,
trig_a_i
=>
ttl_trigs
(
i
),
trig_a_i
=>
ttl_trigs
(
i
),
pulse_err_p_o
=>
open
,
pulse_err_p_o
=>
open
,
pulse_o
=>
ttl_pulses
(
i
)
pulse_o
=>
ttl_pulses
(
i
)
);
);
end
generate
gen_ttl_pulse_gens
;
end
generate
gen_ttl_pulse_gens
;
-- Assign the FPGA outputs for the TTL channels
-- Assign the FPGA outputs for the TTL channels
ttl_o
<=
ttl_pulses
(
5
downto
0
);
ttl_o
<=
ttl_pulses
(
5
downto
0
);
inv_o
<=
ttl_pulses
(
9
downto
6
);
inv_o
<=
ttl_pulses
(
9
downto
6
);
-- Implement the pulse counter registers for the TTL channels
-- Implement the pulse counter registers for the TTL channels
gen_ttl_pulse_cntrs
:
for
i
in
0
to
9
generate
gen_ttl_pulse_cntrs
:
for
i
in
0
to
9
generate
-- First, some rising-edge detectors for output pulses
-- First, some rising-edge detectors for output pulses
p_ttl_pulse_redge
:
process
(
clk_20_i
)
p_ttl_pulse_redge
:
process
(
clk_20_i
)
begin
begin
if
rising_edge
(
clk_20_i
)
then
if
rising_edge
(
clk_20_i
)
then
if
(
rst_20_n
=
'0'
)
then
if
(
rst_20_n
=
'0'
)
then
ttl_pulses_d0
(
i
)
<=
'0'
;
ttl_pulses_d0
(
i
)
<=
'0'
;
ttl_pulses_redge_p
(
i
)
<=
'0'
;
ttl_pulses_redge_p
(
i
)
<=
'0'
;
else
else
ttl_pulses_d0
(
i
)
<=
ttl_pulses
(
i
);
ttl_pulses_d0
(
i
)
<=
ttl_pulses
(
i
);
ttl_pulses_redge_p
(
i
)
<=
ttl_pulses
(
i
)
and
(
not
ttl_pulses_d0
(
i
));
ttl_pulses_redge_p
(
i
)
<=
ttl_pulses
(
i
)
and
(
not
ttl_pulses_d0
(
i
));
end
if
;
end
if
;
end
if
;
end
process
p_ttl_pulse_redge
;
end
if
;
end
process
p_ttl_pulse_redge
;
-- Now, the actual I/O pulse counters
p_ttl_pulse_cnt
:
process
(
clk_20_i
)
begin
if
rising_edge
(
clk_20_i
)
then
if
(
rst_20_n
=
'0'
)
then
opcr
(
i
)
<=
(
others
=>
'0'
);
ipcr
(
i
)
<=
(
others
=>
'0'
);
else
if
(
opcr_ld
(
i
)
=
'1'
)
then
opcr
(
i
)
<=
unsigned
(
opcr_ldval
(
i
));
elsif
(
ttl_pulses_redge_p
(
i
)
=
'1'
)
then
opcr
(
i
)
<=
opcr
(
i
)
+
1
;
end
if
;
if
(
ipcr_ld
(
i
)
=
'1'
)
then
-- Now, the actual I/O pulse counters
ipcr
(
i
)
<=
unsigned
(
ipcr_ldval
(
i
));
p_ttl_pulse_cnt
:
process
(
clk_20_i
)
elsif
(
ttl_trigs_redge_p
(
i
)
=
'1'
)
then
begin
ipcr
(
i
)
<=
ipcr
(
i
)
+
1
;
if
rising_edge
(
clk_20_i
)
then
end
if
;
if
(
rst_20_n
=
'0'
)
then
opcr
(
i
)
<=
(
others
=>
'0'
);
ipcr
(
i
)
<=
(
others
=>
'0'
);
else
if
(
opcr_ld
(
i
)
=
'1'
)
then
opcr
(
i
)
<=
unsigned
(
opcr_ldval
(
i
));
elsif
(
ttl_pulses_redge_p
(
i
)
=
'1'
)
then
opcr
(
i
)
<=
opcr
(
i
)
+
1
;
end
if
;
if
(
ipcr_ld
(
i
)
=
'1'
)
then
ipcr
(
i
)
<=
unsigned
(
ipcr_ldval
(
i
));
elsif
(
ttl_trigs_redge_p
(
i
)
=
'1'
)
then
ipcr
(
i
)
<=
ipcr
(
i
)
+
1
;
end
if
;
end
if
;
end
if
;
end
if
;
end
process
p_ttl_pulse_cnt
;
end
if
;
end
generate
gen_ttl_pulse_cntrs
;
end
process
p_ttl_pulse_cnt
;
-- Process to flash pulse LED when a pulse is output
-- LED flash length: 26 ms
p_pulse_led
:
process
(
clk_20_i
)
is
begin
if
rising_edge
(
clk_20_i
)
then
if
(
rst_20_n
=
'0'
)
then
pulse_led_cnt
(
i
)
<=
(
others
=>
'0'
);
pulse_led
(
i
)
<=
'0'
;
else
case
pulse_led
(
i
)
is
when
'0'
=>
if
(
ttl_pulses_redge_p
(
i
)
=
'1'
)
then
pulse_led
(
i
)
<=
'1'
;
end
if
;
when
'1'
=>
pulse_led_cnt
(
i
)
<=
pulse_led_cnt
(
i
)
+
1
;
if
(
pulse_led_cnt
(
i
)
=
(
pulse_led_cnt
(
i
)
'range
=>
'1'
))
then
pulse_led
(
i
)
<=
'0'
;
end
if
;
when
others
=>
pulse_led
(
i
)
<=
'0'
;
end
case
;
end
if
;
end
if
;
end
process
p_pulse_led
;
end
generate
gen_ttl_pulse_cntrs
;
--============================================================================
--============================================================================
-- Pulse counter registers, retaining values for pulse counters of both RS-485
-- Pulse counter registers, retaining values for pulse counters of both RS-485
...
@@ -1793,8 +1823,9 @@ begin
...
@@ -1793,8 +1823,9 @@ begin
--============================================================================
--============================================================================
-- Drive pulse LEDs
-- Drive pulse LEDs
--============================================================================
--============================================================================
led_front_o
<=
pulse_led_seq
;
led_front_o
<=
not
pulse_led_seq
when
(
pulse_led_en
=
'1'
)
else
led_inv_o
<=
inv_led_seq
;
not
pulse_led
(
5
downto
0
);
led_inv_o
<=
(
others
=>
'0'
);
--inv_led_seq;
led_rear_n_o
<=
not
pulse_led_seq
;
led_rear_n_o
<=
not
pulse_led_seq
;
--============================================================================
--============================================================================
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment