Commit 042ab291 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana

small changes to hdlguide

parent 861d6e9b
......@@ -280,7 +280,7 @@ to buffers and serial resistors and then to the LEDs. The FPGA outputs for lines
are connected to tri-state buffers and the to the LEDs. The FPGA outputs for line
output enables~(L\_OEN) are connected to the output enable of the tri-state buffers.
\begin{figure}
\begin{figure}[hbtp]
\centerline{\includegraphics[width=\textwidth]{fig/bicolor-led}}
\caption{3x2 bicolor LED matrix control}
\label{fig:bicolor-led}
......@@ -329,7 +329,7 @@ for the bicolor status LEDs in the CONV-TTL-BLO firmware.
\label{tbl:bicolor-led-state-conn}
\centerline
{
\begin{tabular}{l c c c c}
\begin{tabular}{l c l c c}
\hline
\textbf{Line} & \textbf{Column} & \multicolumn{1}{c}{\textbf{LED}} & \textbf{LED state bits} & \textbf{Setting}\\
\hline
......@@ -357,12 +357,13 @@ multiplexers are set throughout the logic.
%==============================================================================
% SEC: Pulse gen
%==============================================================================
\pagebreak
\section{Pulse generators}
\label{sec:pulse-gen}
\begin{table}[h]
\caption{Pulse generator blocks}
\label{tbl:pulse-gen}
%\begin{table}[h]
% \caption{Pulse generator blocks}
% \label{tbl:pulse-gen}
\centerline
{
\begin{tabular}{l l l}
......@@ -381,14 +382,14 @@ multiplexers are set throughout the logic.
\hline
\end{tabular}
}
\end{table}
%\end{table}
\vspace*{11pt}
%The \textit{ctb\_pulse\_gen} block generate pulses on the rising edge of the
The \textit{ctb\_pulse\_gen} block generate pulses on the rising edge of the
\textit{trig\_i} input. The pulse width is configurable via the \textit{g\_pulse\_width}
generic. The block also incorporates a glitch filter with a configurable length
(\textit{g\_glitch\_filt\_len}) that can be used to avoid pulses generated because o
(\textit{g\_glitch\_filt\_len}) that can be used to avoid pulses generated because of
glitches at the \textit{trig\_i} input.
These blocks are twice used in the CONV-TTL-BLO firmware. First, they are used for
......@@ -607,7 +608,7 @@ part of the CONV-TTL-BLO project are present in their own folders as sub-nodes o
\textit{doc/} sub-folder. The I$^2$C bridge module folder also contains the instantiated
\textit{i2c\_slave.vhd} file (see \textcolor{red}{\textbf{REFERENCE TO ELMA\_I2C}}) and the documentation for it.
The \textit{release/} folder is the main folder in the firmware pack, as can be seen from the
The \textit{release/} folder is the main folder in the firmware package, as can be seen from the
fact that it is bolded in the folder structure above. It contains top-level files in the
\textit{top/} folder (HDL and UCF file for pin definitions) and other specific modules in
the \textit{rtl/} folder.
......
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