Commit b7f404e0 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana

elma_i2c is now named vbcp_wb

made the necessary changes in
- source files
- vbcp_wb doc
- hdlguide
parent 8fe29359
...@@ -168,9 +168,9 @@ ...@@ -168,9 +168,9 @@
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...@@ -313,64 +313,58 @@ ...@@ -313,64 +313,58 @@
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xml:space="preserve" xml:space="preserve"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans" style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
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style="font-size:9px;font-weight:bold">I<tspan style="font-size:9px;font-weight:bold">VBCP bridge</tspan></text>
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...@@ -489,7 +483,7 @@ ...@@ -489,7 +483,7 @@
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......
...@@ -43,6 +43,7 @@ ...@@ -43,6 +43,7 @@
04-07-2013 & 0.1 & First draft \\ 04-07-2013 & 0.1 & First draft \\
26-07-2013 & 0.2 & Second draft \\ 26-07-2013 & 0.2 & Second draft \\
07-08-2013 & 1.02 & Added pulse rejection to \textit{ctb\_pulse\_gen} \\ 07-08-2013 & 1.02 & Added pulse rejection to \textit{ctb\_pulse\_gen} \\
14-08-2013 & 1.02 & Changed name of \textit{elma\_i2c} to \textit{vbcp\_wb} \\
\hline \hline
\end{tabular} \end{tabular}
} }
...@@ -88,7 +89,7 @@ the CONV-TTL-BLO capabilities: ...@@ -88,7 +89,7 @@ the CONV-TTL-BLO capabilities:
\begin{itemize} \begin{itemize}
\item pulse detection (on pulse rising edge) \item pulse detection (on pulse rising edge)
\item fixed-width pulse generation \item fixed-width pulse generation
\item status retrieval via I$^2$C and the ELMA protocol \item status retrieval via I$^2$C and VBCP
\end{itemize} \end{itemize}
Figure~\ref{fig:hdl-bd} shows a simplified block diagram of the HDL firmware. Each of the Figure~\ref{fig:hdl-bd} shows a simplified block diagram of the HDL firmware. Each of the
...@@ -503,13 +504,13 @@ The complete memory map of the firmware can be found in Appendix~\ref{app:memmap ...@@ -503,13 +504,13 @@ The complete memory map of the firmware can be found in Appendix~\ref{app:memmap
%------------------------------------------------------------------------------ %------------------------------------------------------------------------------
% SUBSEC: Statregs % SUBSEC: Statregs
%------------------------------------------------------------------------------ %------------------------------------------------------------------------------
\subsection{I$^2$C to Wishbone bridge} \subsection{VBCP to Wishbone bridge}
\label{sec:elma-i2c} \label{sec:elma-i2c}
The \textit{elma\_i2c} module implements a bridge between the serial lines on the The \textit{vbcp\_wb} module implements a bridge between the serial lines on the
VME P1 connector using the ELMA I$^2$C-based protocol~\cite{sysmon-i2c}, and the VME P1 connector using VBCP~\cite{sysmon-i2c}, and the Wishbone interconnect.
Wishbone interconnect. The module provides one I$^2$C slave interface for connecting The module provides one I$^2$C slave interface for connecting to an ELMA SysMon
to an ELMA SysMon and one Wishbone master interface. and one Wishbone master interface.
Details about the module's implementation can be found in its documentation. Details about the module's implementation can be found in its documentation.
...@@ -586,12 +587,12 @@ The folder structure used within the firmware is presented below. ...@@ -586,12 +587,12 @@ The folder structure used within the firmware is presented below.
\item \textit{reset\_gen.vhd} \item \textit{reset\_gen.vhd}
\end{itemize} \end{itemize}
\end{itemize} \end{itemize}
\item elma\_i2c/ \item vbcp\_wb/
\begin{itemize} \begin{itemize}
\item rtl/ \item rtl/
\begin{itemize} \begin{itemize}
\item \textit{i2c\_slave.vhd} \item \textit{i2c\_slave.vhd}
\item \textit{elma\_i2c.vhd} \item \textit{vbcp\_wb.vhd}
\end{itemize} \end{itemize}
\end{itemize} \end{itemize}
\end{itemize} \end{itemize}
...@@ -648,7 +649,7 @@ ious signals are declared. ...@@ -648,7 +649,7 @@ ious signals are declared.
The body of the architecture is organised as shown in in Figure~\ref{fig:body}. It begins The body of the architecture is organised as shown in in Figure~\ref{fig:body}. It begins
by instantiating a differential buffer for the 125~MHz system clock and instantiating the by instantiating a differential buffer for the 125~MHz system clock and instantiating the
\textit{reset\_gen} component. Then, the \textit{elma\_i2c} bridge module is instantiated \textit{reset\_gen} component. Then, the \textit{vbcp\_wb} bridge module is instantiated
along with the Wishbone crossbar that offers access to the rest of the Wishbone modules in along with the Wishbone crossbar that offers access to the rest of the Wishbone modules in
the design. Next, the CONV board CSR module is instantiated, followed by the instantiation the design. Next, the CONV board CSR module is instantiated, followed by the instantiation
of twelve pulse generator modules, six for pulse repetition and six for the pulse LEDs. of twelve pulse generator modules, six for pulse repetition and six for the pulse LEDs.
......
FILE=elma_i2c FILE=vbcp_wb
all: all:
pdflatex -synctex=1 -interaction=nonstopmode $(FILE).tex *.tex pdflatex -synctex=1 -interaction=nonstopmode $(FILE).tex *.tex
......
...@@ -67,9 +67,9 @@ ...@@ -67,9 +67,9 @@
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......
...@@ -5,7 +5,7 @@ ...@@ -5,7 +5,7 @@
%--------------------------------------------------------------- %---------------------------------------------------------------
% title % title
%--------------------------------------------------------------- %---------------------------------------------------------------
\noindent{\LARGE \textbf{ELMA I$^2$C to Wishbone bridge}} \noindent{\LARGE \textbf{VBCP to Wishbone bridge}}
\noindent \rule{\textwidth}{.1cm} \noindent \rule{\textwidth}{.1cm}
......
This diff is collapsed.
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "conv_ttl_blo"
syn_project = "conv_ttl_blo.xise"
modules = {
"local" : [
"../top"
]
}
This diff is collapsed.
This diff is collapsed.
PROMGEN: Xilinx Prom Generator P.28xd
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
promgen -spi -w -u 0 conv_ttl_blo.bit
PROM conv_ttl_blo.prm map: Tue Aug 13 16:17:11 2013
Format Mcs86 (32-bit)
Size 2048K
PROM start 0000:0000
PROM end 001f:ffff
Addr1 Addr2 Date File(s)
0000:0000 0016:a673 Aug 13 16:15:17 2013 conv_ttl_blo.bit
This diff is collapsed.
<?xml version="1.0"?>
<Project Version="4" Minor="36">
<FileSet Dir="sources_1" File="fileset.xml"/>
<FileSet Dir="constrs_1" File="fileset.xml"/>
<FileSet Dir="sim_1" File="fileset.xml"/>
<RunSet Dir="runs" File="runs.xml"/>
<DefaultLaunch Dir="$PRUNDIR"/>
<DefaultPromote Dir="$PROMOTEDIR"/>
<Config>
<Option Name="Id" Val="e86760636aa04032b3f8aebe5c67672c"/>
<Option Name="Part" Val="xc6slx45tfgg484-3"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compxlib"/>
<Option Name="TargetLanguage" Val="VHDL"/>
<Option Name="TargetSimulator" Val="ISim"/>
<Option Name="Board" Val=""/>
<Option Name="SourceMgmtMode" Val="DisplayOnly"/>
<Option Name="ActiveSimSet" Val=""/>
<Option Name="CxlOverwriteLibs" Val="1"/>
<Option Name="CxlFuncsim" Val="1"/>
<Option Name="CxlTimesim" Val="1"/>
<Option Name="CxlCore" Val="1"/>
<Option Name="CxlEdk" Val="0"/>
<Option Name="CxlExcludeCores" Val="1"/>
<Option Name="CxlExcludeSubLibs" Val="0"/>
</Config>
</Project>
project open conv_ttl_blo.xise
process run {Generate Programming File} -force rerun_all
files = [
"conv_ttl_blo.ucf",
"conv_ttl_blo.vhd"
]
modules = {
"local" : [
"../../reset_gen",
"../../bicolor_led_ctrl",
"../../vbcp_wb"
],
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git"
]
}
fetchto = "../../../../../ip_cores"
This diff is collapsed.
This diff is collapsed.
...@@ -42,9 +42,9 @@ FILES := ../top/conv_ttl_blo.ucf \ ...@@ -42,9 +42,9 @@ FILES := ../top/conv_ttl_blo.ucf \
../../bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd \ ../../bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd \
../../bicolor_led_ctrl/bicolor_led_ctrl.vhd \ ../../bicolor_led_ctrl/bicolor_led_ctrl.vhd \
../../reset_gen/rtl/reset_gen.vhd \ ../../reset_gen/rtl/reset_gen.vhd \
../../elma_i2c/rtl/i2c_slave_pkg.vhd \ ../../vbcp_wb/rtl/i2c_slave_pkg.vhd \
../../elma_i2c/rtl/i2c_slave.vhd \ ../../vbcp_wb/rtl/i2c_slave.vhd \
../../elma_i2c/rtl/elma_i2c.vhd \ ../../vbcp_wb/rtl/vbcp_wb.vhd \
../../glitch_filt/rtl/glitch_filt.vhd \ ../../glitch_filt/rtl/glitch_filt.vhd \
../../ctb_pulse_gen/rtl/ctb_pulse_gen.vhd \ ../../ctb_pulse_gen/rtl/ctb_pulse_gen.vhd \
../../rtm_detector/rtl/rtm_detector.vhd \ ../../rtm_detector/rtl/rtm_detector.vhd \
......
...@@ -72,34 +72,35 @@ ...@@ -72,34 +72,35 @@
</files> </files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"> <transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1375896857" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1375896857"> <transform xil_pn:end_ts="1376471978" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1376471978">
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<status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1375896857" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1700432985017783241" xil_pn:start_ts="1375896857"> <transform xil_pn:end_ts="1376471978" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1700432985017783241" xil_pn:start_ts="1376471978">
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<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1375896876" xil_pn:in_ck="4832372736998027881" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8267614965335338665" xil_pn:start_ts="1375896857"> <transform xil_pn:end_ts="1376471999" xil_pn:in_ck="-159470544935230363" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8267614965335338665" xil_pn:start_ts="1376471978">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
...@@ -117,11 +118,11 @@ ...@@ -117,11 +118,11 @@
<outfile xil_pn:name="webtalk_pn.xml"/> <outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/> <outfile xil_pn:name="xst"/>
</transform> </transform>
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<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1375896886" xil_pn:in_ck="4600148398000832553" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7879307074684351365" xil_pn:start_ts="1375896876"> <transform xil_pn:end_ts="1376472010" xil_pn:in_ck="4600148398000832553" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7879307074684351365" xil_pn:start_ts="1376471999">
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<outfile xil_pn:name="_ngo"/> <outfile xil_pn:name="_ngo"/>
...@@ -130,7 +131,7 @@ ...@@ -130,7 +131,7 @@
<outfile xil_pn:name="conv_ttl_blo.ngd"/> <outfile xil_pn:name="conv_ttl_blo.ngd"/>
<outfile xil_pn:name="conv_ttl_blo_ngdbuild.xrpt"/> <outfile xil_pn:name="conv_ttl_blo_ngdbuild.xrpt"/>
</transform> </transform>
<transform xil_pn:end_ts="1375896940" xil_pn:in_ck="4600148398000832554" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1375896886"> <transform xil_pn:end_ts="1376472062" xil_pn:in_ck="4600148398000832554" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1376472010">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/> <outfile xil_pn:name="_xmsgs/map.xmsgs"/>
...@@ -143,7 +144,7 @@ ...@@ -143,7 +144,7 @@
<outfile xil_pn:name="conv_ttl_blo_summary.xml"/> <outfile xil_pn:name="conv_ttl_blo_summary.xml"/>
<outfile xil_pn:name="conv_ttl_blo_usage.xml"/> <outfile xil_pn:name="conv_ttl_blo_usage.xml"/>
</transform> </transform>
<transform xil_pn:end_ts="1375896995" xil_pn:in_ck="-9057307156948659133" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1375896940"> <transform xil_pn:end_ts="1376472115" xil_pn:in_ck="-9057307156948659133" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1376472062">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/> <outfile xil_pn:name="_xmsgs/par.xmsgs"/>
...@@ -157,7 +158,7 @@ ...@@ -157,7 +158,7 @@
<outfile xil_pn:name="conv_ttl_blo_pad.txt"/> <outfile xil_pn:name="conv_ttl_blo_pad.txt"/>
<outfile xil_pn:name="conv_ttl_blo_par.xrpt"/> <outfile xil_pn:name="conv_ttl_blo_par.xrpt"/>
</transform> </transform>
<transform xil_pn:end_ts="1375897030" xil_pn:in_ck="-336926714118358808" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1375896995"> <transform xil_pn:end_ts="1376472151" xil_pn:in_ck="-336926714118358808" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1376472115">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
...@@ -169,7 +170,7 @@ ...@@ -169,7 +170,7 @@
<outfile xil_pn:name="webtalk.log"/> <outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/> <outfile xil_pn:name="webtalk_pn.xml"/>
</transform> </transform>
<transform xil_pn:end_ts="1375896995" xil_pn:in_ck="4600148398000832422" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1375896984"> <transform xil_pn:end_ts="1376472115" xil_pn:in_ck="4600148398000832422" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1376472104">
<status xil_pn:value="FailedRun"/> <status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/> <outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......
...@@ -351,13 +351,13 @@ ...@@ -351,13 +351,13 @@
<file xil_pn:name="../../reset_gen/rtl/reset_gen.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../reset_gen/rtl/reset_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="6"/> <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file> </file>
<file xil_pn:name="../../elma_i2c/rtl/i2c_slave_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../vbcp_wb/rtl/i2c_slave_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="7"/> <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file> </file>
<file xil_pn:name="../../elma_i2c/rtl/i2c_slave.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../vbcp_wb/rtl/i2c_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="8"/> <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file> </file>
<file xil_pn:name="../../elma_i2c/rtl/elma_i2c.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../vbcp_wb/rtl/vbcp_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="9"/> <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file> </file>
<file xil_pn:name="../../glitch_filt/rtl/glitch_filt.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../glitch_filt/rtl/glitch_filt.vhd" xil_pn:type="FILE_VHDL">
......
...@@ -7,7 +7,7 @@ modules = { ...@@ -7,7 +7,7 @@ modules = {
"local" : [ "local" : [
"../../reset_gen", "../../reset_gen",
"../rtl", "../rtl",
"../../elma_i2c", "../../vbcp_wb",
"../../ctb_pulse_gen", "../../ctb_pulse_gen",
"../../rtm_detector", "../../rtm_detector",
"../../bicolor_led_ctrl", "../../bicolor_led_ctrl",
......
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
-- CERN (BE-CO-HT) -- CERN (BE-CO-HT)
-- Top level entity of CONV-TTL-BLO V2 -- Top level entity of CONV-TTL-BLO
-- http://www.ohwr.org/projects/conv-ttl-blo -- http://www.ohwr.org/projects/conv-ttl-blo
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
-- --
...@@ -10,7 +10,7 @@ ...@@ -10,7 +10,7 @@
-- --
-- version: 1.0 -- version: 1.0
-- --
-- description: Top entity of CONV-TTL-BLO V1 -- description: Top entity of CONV-TTL-BLO
-- --
-- dependencies: -- dependencies:
-- --
...@@ -31,12 +31,12 @@ ...@@ -31,12 +31,12 @@
-- received a copy of the GNU Lesser General Public License along with this -- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html -- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
library IEEE; library ieee;
library unisim; library unisim;
use IEEE.STD_LOGIC_1164.ALL; use ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.ALL; use ieee.numeric_std.all;
use UNISIM.VCOMPONENTS.ALL; use unisim.vcomponents.all;
use work.bicolor_led_ctrl_pkg.all; use work.bicolor_led_ctrl_pkg.all;
use work.wishbone_pkg.all; use work.wishbone_pkg.all;
...@@ -241,7 +241,7 @@ architecture behav of conv_ttl_blo is ...@@ -241,7 +241,7 @@ architecture behav of conv_ttl_blo is
-- I2C bridge -- I2C bridge
-- (use: convert I2C transfers into WB transfers on memmapped registers) -- (use: convert I2C transfers into WB transfers on memmapped registers)
component elma_i2c is component vbcp_wb is
port port
( (
-- Clock, reset -- Clock, reset
...@@ -273,7 +273,7 @@ architecture behav of conv_ttl_blo is ...@@ -273,7 +273,7 @@ architecture behav of conv_ttl_blo is
wbm_rty_i : in std_logic; wbm_rty_i : in std_logic;
wbm_err_i : in std_logic wbm_err_i : in std_logic
); );
end component elma_i2c; end component vbcp_wb;
component conv_regs is component conv_regs is
port ( port (
...@@ -419,8 +419,8 @@ begin ...@@ -419,8 +419,8 @@ begin
-- Set the I2C address signal according to ELMA protocol [1] -- Set the I2C address signal according to ELMA protocol [1]
i2c_addr <= "10" & fpga_ga_i; i2c_addr <= "10" & fpga_ga_i;
-- Instantiate I2C bridge component -- Instantiate VBCP bridge component
cmp_i2c_bridge : elma_i2c cmp_i2c_bridge : vbcp_wb
port map port map
( (
-- Clock, reset -- Clock, reset
......
files = [ files = [
"i2c_slave_pkg.vhd", "i2c_slave_pkg.vhd",
"i2c_slave.vhd", "i2c_slave.vhd",
"elma_i2c.vhd" "vbcp_wb.vhd"
] ]
modules = { modules = {
......
--============================================================================== --==============================================================================
-- CERN (BE-CO-HT) -- CERN (BE-CO-HT)
-- I2C to Wishbone bridge for VME64x crates -- VME Board Control Protocol (VBCP) to Wishbone bridge for VME64x crates
--============================================================================== --==============================================================================
-- --
-- author: Theodor Stana (t.stana@cern.ch) -- author: Theodor Stana (t.stana@cern.ch)
...@@ -58,7 +58,7 @@ use ieee.numeric_std.all; ...@@ -58,7 +58,7 @@ use ieee.numeric_std.all;
use work.i2c_slave_pkg.all; use work.i2c_slave_pkg.all;
entity elma_i2c is entity vbcp_wb is
port port
( (
-- Clock, reset -- Clock, reset
...@@ -90,9 +90,9 @@ entity elma_i2c is ...@@ -90,9 +90,9 @@ entity elma_i2c is
wbm_rty_i : in std_logic; wbm_rty_i : in std_logic;
wbm_err_i : in std_logic wbm_err_i : in std_logic
); );
end entity elma_i2c; end entity vbcp_wb;
architecture behav of elma_i2c is architecture behav of vbcp_wb is
--============================================================================ --============================================================================
-- Type declarations -- Type declarations
......
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