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C
Conv TTL Blocking - Gateware
Commit b7f404e0 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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elma_i2c is now named vbcp_wb 

made the necessary changes in
- source files
- vbcp_wb doc
- hdlguide
parent 8fe29359
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doc/hdlguide/fig/hdl-bd.svg
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......@@ -168,9 +168,9 @@
borderopacity="1.0"
inkscape:pageopacity="0.0"
inkscape:pageshadow="2"
inkscape:zoom="3.959798"
inkscape:cx="468.2635"
inkscape:cy="210.26842"
inkscape:zoom="2.8"
inkscape:cx="253.43677"
inkscape:cy="54.646428"
inkscape:document-units="px"
inkscape:current-layer="layer1"
showgrid="true"
......@@ -206,7 +206,7 @@
<dc:format>image/svg+xml</dc:format>
<dc:type
rdf:resource="http://purl.org/dc/dcmitype/StillImage" />
<dc:title></dc:title>
<dc:title />
</cc:Work>
</rdf:RDF>
</metadata>
......@@ -313,64 +313,58 @@
<text
xml:space="preserve"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="243.93141"
x="234.37108"
y="322.44095"
id="text2989"
sodipodi:linespacing="125%"><tspan
sodipodi:role="line"
id="tspan2991"
x="243.93141"
x="234.37108"
y="322.44095"
style="font-size:9px;font-weight:bold">I<tspan
style="font-size:9px;font-weight:bold">VBCP bridge</tspan></text>
<rect
style="fill:#cccccc;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:1;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;stroke-dashoffset:0"
id="rect2987"
width="88.58268"
height="35.433071"
x="221.4567"
y="325.98422"
rx="0"
ry="0" />
<text
xml:space="preserve"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="225"
y="341.79211"
id="text2993"
sodipodi:linespacing="125%"><tspan
sodipodi:role="line"
id="tspan2995"
x="225"
y="341.79211">I<tspan
style="font-size:65.00091553%;baseline-shift:super"
id="tspan13661">2</tspan>C bridge</tspan></text>
<g
transform="translate(8.8582768,212.59843)"
id="g3800">
<rect
ry="0"
rx="0"
y="113.3858"
x="212.59842"
height="35.433071"
width="88.58268"
id="rect2987"
style="fill:#d9d9d9;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:1;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;stroke-dashoffset:0" />
<text
sodipodi:linespacing="125%"
id="text2993"
y="129.19368"
x="216.14172"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
y="129.19368"
x="216.14172"
id="tspan2995"
sodipodi:role="line">I<tspan
id="tspan2999"
style="font-size:65.00091553%;baseline-shift:super">2</tspan>C</tspan><tspan
id="tspan2997"
y="141.69368"
x="216.14172"
sodipodi:role="line">slave</tspan></text>
<text
xml:space="preserve"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="298.52597"
y="128.42656"
id="text3001"
sodipodi:linespacing="125%"><tspan
style="text-align:end;text-anchor:end"
sodipodi:role="line"
x="301.70956"
y="128.42656"
id="tspan3007">WB </tspan><tspan
style="text-align:end;text-anchor:end"
id="tspan3012"
sodipodi:role="line"
x="298.52597"
y="140.92656">master</tspan></text>
</g>
id="tspan2999">2</tspan>C</tspan><tspan
sodipodi:role="line"
x="225"
y="354.29211"
id="tspan2997">slave</tspan></text>
<text
sodipodi:linespacing="125%"
id="text3001"
y="341.02499"
x="307.38425"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
id="tspan3007"
y="341.02499"
x="310.56784"
sodipodi:role="line"
style="text-align:end;text-anchor:end">WB </tspan><tspan
y="353.52499"
x="307.38425"
sodipodi:role="line"
id="tspan3012"
style="text-align:end;text-anchor:end">master</tspan></text>
<path
style="fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;marker-start:none;marker-end:none"
d="m 159.44882,334.8425 62.00787,-0.0464 0,0 0,0"
......@@ -489,7 +483,7 @@
height="50.1063"
width="62.007874"
id="rect4677"
style="fill:#d9d9d9;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:1;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;stroke-dashoffset:0" />
style="fill:#cccccc;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:1;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;stroke-dashoffset:0" />
<g
id="g5332"
transform="translate(-40.666191,77.702441)">
......
doc/hdlguide/hdlguide-conv-ttl-blo.tex
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......@@ -43,6 +43,7 @@
04-07-2013 & 0.1 & First draft \\
26-07-2013 & 0.2 & Second draft \\
07-08-2013 & 1.02 & Added pulse rejection to \textit{ctb\_pulse\_gen} \\
14-08-2013 & 1.02 & Changed name of \textit{elma\_i2c} to \textit{vbcp\_wb} \\
\hline
\end{tabular}
}
......@@ -88,7 +89,7 @@ the CONV-TTL-BLO capabilities:
\begin{itemize}
\item pulse detection (on pulse rising edge)
\item fixed-width pulse generation
\item status retrieval via I$^2$C and the ELMA protocol
\item status retrieval via I$^2$C and VBCP
\end{itemize}
Figure~\ref{fig:hdl-bd} shows a simplified block diagram of the HDL firmware. Each of the
......@@ -503,13 +504,13 @@ The complete memory map of the firmware can be found in Appendix~\ref{app:memmap
%------------------------------------------------------------------------------
% SUBSEC: Statregs
%------------------------------------------------------------------------------
\subsection{I$^2$C to Wishbone bridge}
\subsection{VBCP to Wishbone bridge}
\label{sec:elma-i2c}
The \textit{elma\_i2c} module implements a bridge between the serial lines on the
VME P1 connector using the ELMA I$^2$C-based protocol~\cite{sysmon-i2c}, and the
Wishbone interconnect. The module provides one I$^2$C slave interface for connecting
to an ELMA SysMon and one Wishbone master interface.
The \textit{vbcp\_wb} module implements a bridge between the serial lines on the
VME P1 connector using VBCP~\cite{sysmon-i2c}, and the Wishbone interconnect.
The module provides one I$^2$C slave interface for connecting to an ELMA SysMon
and one Wishbone master interface.
Details about the module's implementation can be found in its documentation.
......@@ -586,12 +587,12 @@ The folder structure used within the firmware is presented below.
\item \textit{reset\_gen.vhd}
\end{itemize}
\end{itemize}
\item elma\_i2c/
\item vbcp\_wb/
\begin{itemize}
\item rtl/
\begin{itemize}
\item \textit{i2c\_slave.vhd}
\item \textit{elma\_i2c.vhd}
\item \textit{vbcp\_wb.vhd}
\end{itemize}
\end{itemize}
\end{itemize}
......@@ -648,7 +649,7 @@ ious signals are declared.
The body of the architecture is organised as shown in in Figure~\ref{fig:body}. It begins
by instantiating a differential buffer for the 125~MHz system clock and instantiating the
\textit{reset\_gen} component. Then, the \textit{elma\_i2c} bridge module is instantiated
\textit{reset\_gen} component. Then, the \textit{vbcp\_wb} bridge module is instantiated
along with the Wishbone crossbar that offers access to the rest of the Wishbone modules in
the design. Next, the CONV board CSR module is instantiated, followed by the instantiation
of twelve pulse generator modules, six for pulse repetition and six for the pulse LEDs.
......
doc/elma_i2c/Makefile → doc/vbcp_wb/Makefile
View file @ b7f404e0
FILE=elma_i2c
FILE=vbcp_wb
all:
pdflatex -synctex=1 -interaction=nonstopmode $(FILE).tex *.tex
......
doc/elma_i2c/fig/sys.svg → doc/vbcp_wb/fig/sys.svg
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borderopacity="1.0"
inkscape:pageopacity="0.0"
inkscape:pageshadow="2"
inkscape:zoom="1.4"
inkscape:cx="142.2339"
inkscape:cy="34.318633"
inkscape:zoom="2.8"
inkscape:cx="266.19801"
inkscape:cy="49.556734"
inkscape:document-units="px"
inkscape:current-layer="layer1"
showgrid="true"
......@@ -269,14 +269,14 @@
sodipodi:linespacing="125%"
id="text4957"
y="204.5881"
x="431.07422"
x="431.36719"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
style="font-size:10px;font-weight:bold;fill:#000000;fill-opacity:1"
y="204.5881"
x="431.07422"
x="431.36719"
id="tspan4959"
sodipodi:role="line">elma_i2c</tspan></text>
sodipodi:role="line">vbcp_wb</tspan></text>
<path
style="fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;marker-start:url(#TriangleInM);marker-end:url(#TriangleOutM)"
d="m 488.97638,201.96848 14.17323,0"
......
doc/elma_i2c/title.tex → doc/vbcp_wb/title.tex
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......@@ -5,7 +5,7 @@
%---------------------------------------------------------------
% title
%---------------------------------------------------------------
\noindent{\LARGE \textbf{ELMA I$^2$C to Wishbone bridge}}
\noindent{\LARGE \textbf{VBCP to Wishbone bridge}}
\noindent \rule{\textwidth}{.1cm}
......
doc/elma_i2c/elma_i2c.tex → doc/vbcp_wb/vbcp_wb.tex
View file @ b7f404e0
......@@ -41,6 +41,7 @@
\multicolumn{1}{c}{\textbf{Date}} & \multicolumn{1}{c}{\textbf{Version}} & \multicolumn{1}{c}{\textbf{Change}} \\
\hline
26-06-2013 & 0.01 & First draft \\
14-08-2013 & 0.02 & Second draft \\
\hline
\end{tabular}
}
......@@ -60,7 +61,7 @@
\section*{List of Abbreviations}
\begin{tabular}{l l}
FSM & Finite-State Machine \\
I$^2$C & Inter-Integrated Circuit (bus) \\
VBCP & Inter-Integrated Circuit (bus) \\
SysMon & ELMA crate System Monitor board \\
VME & VERSAmodule Eurocard \\
\end{tabular}
......@@ -75,23 +76,23 @@
\section{Introduction}
\label{sec:intro}
This document describes the \textit{elma\_i2c} module, an I$^2$C to Wishbone
This document describes the \textit{vbcp\_wb} module, a VME Board Control Protocol (VBCP) to Wishbone
bridge HDL core for VME64x crates from ELMA. These crates offer the possibility of accessing
boards in VME slots via either VME, or I$^2$C. Boards not using the VME lines
on a slot can implement the \textit{elma\_i2c} module on an FPGA; implements an
I$^2$C slave and translates I$^2$C accesses into Wishbone \cite{wb-spec} accesses to a
boards in VME slots via either VME, or VBCP. Boards not using the VME lines
on a slot can implement the \textit{vbcp\_wb} module on an FPGA; implements an
VBCP slave and translates VBCP accesses into Wishbone \cite{wb-spec} accesses to a
Wishbone slave device.
A typical system where the \textit{elma\_i2c} module is employed is shown in
A typical system where the \textit{vbcp\_wb} module is employed is shown in
Figure~\ref{fig:sys}. ELMA VME crates contain a SysMon (system monitor) board~\cite{sysmon},
that is mainly used for monitoring VME voltages and controlling the fans of the VME crate.
The SysMon can be connected to via either a serial connection or Telnet. Then, sending
specific commands (see Section \ref{sec:testing}) via one of the two are translated by the
SysMon into I$^2$C accesses following the protocol described in Section~\ref{sec:elma-i2c}.
SysMon into VBCP accesses following the protocol described in Section~\ref{sec:vbcp}.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/sys}}
\caption{Typical system for the \textit{elma\_i2c} module}
\caption{Typical system for the \textit{vbcp\_wb} module}
\label{fig:sys}
\end{figure}
......@@ -101,13 +102,13 @@ SysMon into I$^2$C accesses following the protocol described in Section~\ref{sec
\section{Instantiation}
\label{sec:instantiation}
The ports of the \textit{elma\_i2c} module are shown in Table~\ref{tbl:ports}.
The ports of the \textit{vbcp\_wb} module are shown in Table~\ref{tbl:ports}.
The I$^2$C signals should be connected to tri-state ports, as shown in
Figure~\ref{fig:i2c-ports}; Wishbone slaves should be connected to the
Wishbone master interface ports, prefixed with \textit{wbm}.
\begin{table}[h]
\caption{Ports of \textit{elma\_i2c} module}
\caption{Ports of \textit{vbcp\_wb} module}
\label{tbl:ports}
\centerline
{
......@@ -123,8 +124,8 @@ Wishbone master interface ports, prefixed with \textit{wbm}.
scl\_en\_o & 1 & SCL line tri-state enable \\
scl\_i & 1 & SCL line input \\
scl\_o & 1 & SCL line output \\
i2c\_addr\_i & 7 & I$^2$C slave address on ELMA I$^2$C bus \\
i2c\_done\_o & 1 & High for one clk\_i cycle when an I$^2$C transfer is finished \\
i2c\_addr\_i & 7 & VBCP slave address on ELMA VBCP bus \\
i2c\_done\_o & 1 & High for one clk\_i cycle when an VBCP transfer is finished \\
i2c\_err\_o & 1 & High for one clk\_i cycle when an error occurs in the ELMA protocol
or an attempt is made to access an non-existing register on the
Wishbone bus \\
......@@ -145,12 +146,12 @@ Wishbone master interface ports, prefixed with \textit{wbm}.
\begin{figure}[h]
\centerline{\includegraphics[width=.75\textwidth]{fig/i2c-ports}}
\caption{I$^2$C port external connections}
\caption{VBCP port external connections}
\label{fig:i2c-ports}
\end{figure}
%\begin{table}[h]
% \caption{Wishbone datasheet of \textit{elma\_i2c} module}
% \caption{Wishbone datasheet of \textit{vbcp\_wb} module}
% \label{tbl:wb-ds}
% \centerline
% {
......@@ -158,7 +159,7 @@ Wishbone master interface ports, prefixed with \textit{wbm}.
% \hline
% \multicolumn{1}{c}{\textbf{Description}} & \multicolumn{1}{c}{\textbf{Specification}} \\
% \hline
% General description & ELMA I$^2$C to Wishbone bridge \\
% General description & ELMA VBCP to Wishbone bridge \\
% Supported cycles & Master, read/write \\
% Data port, size & 32-bit \\
% Data port, granularity & 32-bit \\
......@@ -186,7 +187,7 @@ Wishbone master interface ports, prefixed with \textit{wbm}.
%==============================================================================
% SEC: Testing
%==============================================================================
\section{Testing the \textit{elma\_i2c} module}
\section{Testing the \textit{vbcp\_wb} module}
\label{sec:testing}
After proper synthesis and download to the FPGA, a Telnet or serial connection
......@@ -203,7 +204,7 @@ and \textit{writereg}, outlined in Table~\ref{tbl:cmds}.
\hline
\multicolumn{1}{c}{\textbf{Command}} & \multicolumn{1}{c}{\textbf{Description}} \\
\hline
writereg \textit{slot reg val} & Writes the value \textit{val} to register number
writereg \textit{slot reg val} & Writes the \textit{hex} value \textit{val} to register number
\textit{reg} of board in slot number \textit{slot} \\
readreg \textit{slot reg} & Returns the value of register number \textit{reg} of
board in slot number \textit{slot} \\
......@@ -248,7 +249,7 @@ space 0x00 to 0x20.
The example below shows how to connect to an ELMA crate at IP address 1.2.3.4,
obtaining the value of a register at address 0x10 in a board in VME slot 2,
writing the decimal value 12 to the same register and reading it back to check for
writing the hex value 0x1234 to the same register and reading it back to check for
proper modification.
\begin{verbatim}
......@@ -260,28 +261,32 @@ login:user
password:**********
%>readreg 2 5
Read Data: 00ABCDEF
%>writereg 2 5 12
%>writereg 2 5 1234
Done!
%>readreg 2 5
Read Data: 0000000C
Read Data: 00001234
\end{verbatim}
%==============================================================================
% SEC: Protocol
%==============================================================================
\pagebreak
\section{ELMA I$^2$C Protocol}
\label{sec:elma-i2c}
\section{The VME Board Control Protocol}
\label{sec:vbcp}
Using the I$^2$C lines on the VME P1 connector, one can access boards placed
in a VME crate. For this purpose, ELMA has defined a higher-level protocol~\cite{sysmon-i2c}
that uses I$^2$C as a low-level protocol.
The VME backplane provides two serial lines (\textit{SERCLK} and \textit{SERDAT})
on the P1 connector. These lines can be used to access boards placed in a VME
slots to control them, in cases where the VME interface is not implemented.
The VME Board Control Protocol (VBCP)~\cite{sysmon-i2c} has been defined for such
purposes. Using I$^2$C as a low-level protocol, the bytes of a register can be read
from or written to a VME board.
Figure~\ref{fig:sysmon-wr} shows a write operation from the SysMon to a VME
board. The process starts with the control byte, containing the board's
I$^2$C slave address and the read/write bit cleared, indicating an
I$^2$C write. After the slave's ACK, the following two bytes send the
12-bit address in little-endian order (most significant byte first).
12-bit register address in little-endian order (most significant byte first).
After the address has been acknowledged, the following four I$^2$C transfers
are used to transmit the 32-bit data to be written to the board register.
Data transmission occurs in big-endian order (least significant byte first).
......@@ -293,7 +298,7 @@ Data transmission occurs in big-endian order (least significant byte first).
\end{figure}
\begin{figure}[h]
\centerline{\includegraphics[width=.9\textwidth]{fig/sysmon-rd}}
\centerline{\includegraphics[width=\textwidth]{fig/sysmon-rd}}
\caption{SysMon read operation}
\label{fig:sysmon-rd}
\end{figure}
......@@ -314,7 +319,7 @@ are sent by the VME board in big-endian order.
\label{sec:implem}
In order to perform low-level I$^2$C transfers, the \textit{i2c\_slave} module
\textcolor{red}{REFERENCE?} is instantiated and used within the \textit{elma\_i2c}
\textcolor{red}{REFERENCE?} is instantiated and used within the \textit{vbcp\_wb}
module. The outputs of the \textit{i2c\_slave} module are used as controls
for an eight-state finite state machine (FSM), a simplified version of which
is shown in Figure~\ref{fig:fsm}. Table~\ref{tbl:fsm} also lists the states of
......@@ -322,12 +327,12 @@ the state machine.
\begin{figure}[h]
\centerline{\includegraphics[scale=.65]{fig/fsm}}
\caption{Main FSM of \textit{elma\_i2c} module}
\caption{Main FSM of \textit{vbcp\_wb} module}
\label{fig:fsm}
\end{figure}
\begin{table}[h]
\caption{States of \textit{elma\_i2c} FSM}
\caption{States of \textit{vbcp\_wb} FSM}
\label{tbl:fsm}
\centerline
{
......@@ -335,11 +340,11 @@ the state machine.
\hline
\multicolumn{1}{c}{\textbf{State}} & \multicolumn{1}{c}{\textbf{Description}} \\
\hline
ST\_IDLE & Wait for the \textit{i2c\_slave} module to receive the I$^2$C
ST\_IDLE & Wait for the \textit{i2c\_slave} module to receive the VBCP
address and go to \textit{ST\_WB\_ADR}. The starting value at the
\textit{op\_o} output of the \textit{i2c\_slave} module is stored
for checking in \textit{ST\_OP} \\
ST\_WB\_ADR & Shift in the two address bytes sent via I$^2$C and go to
ST\_WB\_ADR & Shift in the two address bytes sent via VBCP and go to
\textit{ST\_SIM\_WB\_TRANSF} \\
ST\_SIM\_WB\_TRANSF & Start a Wishbone read transfer from address received in previous
state and go to \textit{ST\_OP} if Wishbone address exists (Wishbone
......@@ -347,8 +352,8 @@ the state machine.
received) \\
ST\_OP & Check the \textit{op\_o} output of the \textit{i2c\_slave} module.
If different from the value at the start, go to \textit{ST\_SYSMON\_RD\_WB} state
(SysMon is reading from \textit{elma\_i2c}), otherwise continue shifting
in bytes (SysMon writing to \textit{elma\_i2c}) \\
(SysMon is reading from \textit{vbcp\_wb}), otherwise continue shifting
in bytes (SysMon writing to \textit{vbcp\_wb}) \\
ST\_SYSMON\_WR & Continue reading up to four bytes sent by the SysMon and go to
\textit{ST\_SYSMON\_WR\_WB}\\
ST\_SYSMON\_WR\_WB & Perform a Wishbone write transfer to the register with the address obtained in
......@@ -366,7 +371,7 @@ When the \textit{i2c\_slave} module finishes a transfer (signaled by a \textit{d
the status is checked and if it is as expected (e.g., a \textit{address good} in the
\textit{ST\_IDLE} state), the FSM advances to the next state. It should be noted that where the
SysMon appears in the state names, it indicates what the SysMon action is. For example, if the state
of the FSM is \textit{ST\_SYSMON\_WR}, this means the SysMon is writing and the \textit{elma\_i2c}
of the FSM is \textit{ST\_SYSMON\_WR}, this means the SysMon is writing and the \textit{vbcp\_wb}
is reading.
To better understand how the FSM operates, Figures \ref{fig:sysmon-wr-fsm} and
......@@ -374,7 +379,7 @@ To better understand how the FSM operates, Figures \ref{fig:sysmon-wr-fsm} and
during reads and writes from the SysMon.
When the SysMon writes (Figure~\ref{fig:sysmon-wr-fsm}), the
\textit{elma\_i2c} module waits in the \textit{ST\_IDLE} state until
\textit{vbcp\_wb} module waits in the \textit{ST\_IDLE} state until
the I$^2$C address is received, then, while in the \textit{ST\_WB\_ADR} state,
it shifts in the Wishbone address. A Wishbone transfer is then simulated with
the received the address and if this address exists (a Wishbone \textit{ack}
......@@ -389,18 +394,18 @@ reading from a board, however, the I$^2$C transfer is restarted and the order
is reversed (SysMon starts reading). Thus, while in \textit{ST\_OP}, the FSM
detects a different value of \textit{op\_o} and goes into the
\textit{ST\_SYSMON\_RD\_WB} state. The value of the register is read here and
sent via I$^2$C in the \textit{ST\_SYSMON\_RD} state.
sent via VBCP in the \textit{ST\_SYSMON\_RD} state.
\pagebreak
\begin{figure}[h]
\centerline{\includegraphics[width=.9\textwidth]{fig/sysmon-wr-fsm}}
\caption{FSM states when the SysMon writes to the \textit{elma\_i2c}}
\caption{FSM states when the SysMon writes to the \textit{vbcp\_wb}}
\label{fig:sysmon-wr-fsm}
\end{figure}
\begin{figure}[h]
\centerline{\includegraphics[width=.9\textwidth]{fig/sysmon-rd-fsm}}
\caption{FSM states when the SysMon reads from the \textit{elma\_i2c}}
\caption{FSM states when the SysMon reads from the \textit{vbcp\_wb}}
\label{fig:sysmon-rd-fsm}
\end{figure}
......@@ -409,6 +414,6 @@ sent via I$^2$C in the \textit{ST\_SYSMON\_RD} state.
%==============================================================================
\pagebreak
\bibliographystyle{ieeetr}
\bibliography{elma_i2c}
\bibliography{vbcp_wb}
\end{document}
hdl/regtest/syn/Makefile 0 → 100644
View file @ b7f404e0
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
PROJECT := conv_ttl_blo.xise
ISE_CRAP := *.b conv_ttl_blo_summary.html *.tcl conv_ttl_blo.bld conv_ttl_blo.cmd_log *.drc conv_ttl_blo.lso *.ncd conv_ttl_blo.ngc conv_ttl_blo.ngd conv_ttl_blo.ngr conv_ttl_blo.pad conv_ttl_blo.par conv_ttl_blo.pcf conv_ttl_blo.prj conv_ttl_blo.ptwx conv_ttl_blo.stx conv_ttl_blo.syr conv_ttl_blo.twr conv_ttl_blo.twx conv_ttl_blo.gise conv_ttl_blo.unroutes conv_ttl_blo.ut conv_ttl_blo.xpi conv_ttl_blo.xst conv_ttl_blo_bitgen.xwbt conv_ttl_blo_envsettings.html conv_ttl_blo_guide.ncd conv_ttl_blo_map.map conv_ttl_blo_map.mrp conv_ttl_blo_map.ncd conv_ttl_blo_map.ngm conv_ttl_blo_map.xrpt conv_ttl_blo_ngdbuild.xrpt conv_ttl_blo_pad.csv conv_ttl_blo_pad.txt conv_ttl_blo_par.xrpt conv_ttl_blo_summary.xml conv_ttl_blo_usage.xml conv_ttl_blo_xst.xrpt usage_statistics_webtalk.html webtalk.log webtalk_pn.xml run.tcl
#target for performing local synthesis
local:
echo "project open $(PROJECT)" > run.tcl
echo "process run {Generate Programming File} -force rerun_all" >> run.tcl
xtclsh run.tcl
#target for cleaing all intermediate stuff
clean:
rm -f $(ISE_CRAP)
rm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo
#target for cleaning final files
mrproper:
rm -f *.bit *.bin *.mcs
USER:=$(HDLMAKE_USER)#take the value from the environment
SERVER:=$(HDLMAKE_SERVER)#take the value from the environment
R_NAME:=conv_ttl_blo
__test_for_remote_synthesis_variables:
ifeq (x$(USER),x)
@echo "Remote synthesis user is not set. You can set it by editing variable USER in the makefile." && false
endif
ifeq (x$(SERVER),x)
@echo "Remote synthesis server is not set. You can set it by editing variable SERVER in the makefile." && false
endif
CWD := $(shell pwd)
FILES := ../top/conv_ttl_blo.ucf \
../top/conv_ttl_blo.vhd \
../../bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd \
../../bicolor_led_ctrl/bicolor_led_ctrl.vhd \
../../reset_gen/rtl/reset_gen.vhd \
../../vbcp_wb/rtl/i2c_slave_pkg.vhd \
../../vbcp_wb/rtl/i2c_slave.vhd \
../../vbcp_wb/rtl/vbcp_wb.vhd \
../../glitch_filt/rtl/glitch_filt.vhd \
../../../../../ip_cores/general-cores/modules/common/gencores_pkg.vhd \
../../../../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd \
../../../../../ip_cores/general-cores/modules/common/gc_moving_average.vhd \
../../../../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd \
../../../../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd \
../../../../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd \
../../../../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd \
../../../../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd \
../../../../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd \
../../../../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd \
../../../../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd \
../../../../../ip_cores/general-cores/modules/common/gc_dual_clock_ram.vhd \
../../../../../ip_cores/general-cores/modules/common/gc_wfifo.vhd \
../../../../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd \
../../../../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd \
../../../../../ip_cores/general-cores/modules/common/gc_word_packer.vhd \
../../../../../ip_cores/general-cores/modules/common/gc_clk_div.vhd \
../../../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd \
../../../../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd \
../../../../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd \
../../../../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd \
../../../../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd \
../../../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd \
../../../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd \
../../../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd \
../../../../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd \
../../../../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd \
../../../../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd \
../../../../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v \
../../../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v \
../../../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v \
../../../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v \
../../../../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v \
../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v \
../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v \
../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v \
../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v \
../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.v \
../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v \
../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.v \
../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v \
../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v \
../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v \
../../../../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_wb.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v \
../../../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v \
../../../../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v \
run.tcl \
conv_ttl_blo.xise
#target for running simulation in the remote location
remote: __test_for_remote_synthesis_variables __send __do_synthesis __send_back
__send_back: __do_synthesis
__do_synthesis: __send
__send: __test_for_remote_synthesis_variables
__send:
ssh $(USER)@$(SERVER) 'mkdir -p $(R_NAME)'
rsync -Rav $(foreach file, $(FILES), $(shell readlink -f $(file))) $(USER)@$(SERVER):$(R_NAME)
__do_synthesis:
ssh $(USER)@$(SERVER) 'cd $(R_NAME)$(CWD) && xtclsh run.tcl'
__send_back:
cd .. && rsync -av $(USER)@$(SERVER):$(R_NAME)$(CWD) . && cd $(CWD)
#target for removing stuff from the remote location
cleanremote:
ssh $(USER)@$(SERVER) 'rm -rf $(R_NAME)'
hdl/regtest/syn/Manifest.py 0 → 100644
View file @ b7f404e0
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "conv_ttl_blo"
syn_project = "conv_ttl_blo.xise"
modules = {
"local" : [
"../top"
]
}
hdl/regtest/syn/conv_ttl_blo.gise 0 → 100644
View file @ b7f404e0
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="conv_ttl_blo.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="conv_ttl_blo.bgn" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="conv_ttl_blo.bit" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="conv_ttl_blo.bld"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="conv_ttl_blo.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_DRC" xil_pn:name="conv_ttl_blo.drc" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="conv_ttl_blo.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="conv_ttl_blo.ncd" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="conv_ttl_blo.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="conv_ttl_blo.ngd"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="conv_ttl_blo.ngr"/>
<file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="conv_ttl_blo.pad"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="conv_ttl_blo.par" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="conv_ttl_blo.pcf" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="conv_ttl_blo.prj"/>
<file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="conv_ttl_blo.ptwx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="conv_ttl_blo.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="conv_ttl_blo.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="conv_ttl_blo.twr" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="conv_ttl_blo.twx" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="conv_ttl_blo.unroutes" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="conv_ttl_blo.ut" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:fileType="FILE_XPI" xil_pn:name="conv_ttl_blo.xpi"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="conv_ttl_blo.xst"/>
<file xil_pn:fileType="FILE_NCD" xil_pn:name="conv_ttl_blo_guide.ncd" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="conv_ttl_blo_map.map" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="conv_ttl_blo_map.mrp" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="conv_ttl_blo_map.ncd" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="conv_ttl_blo_map.ngm" xil_pn:subbranch="Map"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="conv_ttl_blo_map.xrpt"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="conv_ttl_blo_ngdbuild.xrpt"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="conv_ttl_blo_pad.csv" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="conv_ttl_blo_pad.txt" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="conv_ttl_blo_par.xrpt"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="conv_ttl_blo_summary.xml"/>
<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="conv_ttl_blo_usage.xml"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="conv_ttl_blo_xst.xrpt"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1376471884" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1376471884">
<status xil_pn:value="SuccessfullyRun"/>
</transform>
<transform xil_pn:end_ts="1376471884" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1700432985017783241" xil_pn:start_ts="1376471884">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1376471884" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-5050901284947628582" xil_pn:start_ts="1376471884">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1376471884" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1376471884">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1376471884" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2180482239361632071" xil_pn:start_ts="1376471884">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1376471884" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1376471884">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1376471884" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-6206634123545964380" xil_pn:start_ts="1376471884">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1376471900" xil_pn:in_ck="9111352100311135339" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8267614965335338665" xil_pn:start_ts="1376471884">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="conv_ttl_blo.lso"/>
<outfile xil_pn:name="conv_ttl_blo.ngc"/>
<outfile xil_pn:name="conv_ttl_blo.ngr"/>
<outfile xil_pn:name="conv_ttl_blo.prj"/>
<outfile xil_pn:name="conv_ttl_blo.stx"/>
<outfile xil_pn:name="conv_ttl_blo.syr"/>
<outfile xil_pn:name="conv_ttl_blo.xst"/>
<outfile xil_pn:name="conv_ttl_blo_xst.xrpt"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1376471900" xil_pn:in_ck="3498961748663175870" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3953035127305197084" xil_pn:start_ts="1376471900">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1376471911" xil_pn:in_ck="4600148398000832553" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7879307074684351365" xil_pn:start_ts="1376471900">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<outfile xil_pn:name="conv_ttl_blo.bld"/>
<outfile xil_pn:name="conv_ttl_blo.ngd"/>
<outfile xil_pn:name="conv_ttl_blo_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1376471959" xil_pn:in_ck="4600148398000832554" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1376471911">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<outfile xil_pn:name="conv_ttl_blo.pcf"/>
<outfile xil_pn:name="conv_ttl_blo_map.map"/>
<outfile xil_pn:name="conv_ttl_blo_map.mrp"/>
<outfile xil_pn:name="conv_ttl_blo_map.ncd"/>
<outfile xil_pn:name="conv_ttl_blo_map.ngm"/>
<outfile xil_pn:name="conv_ttl_blo_map.xrpt"/>
<outfile xil_pn:name="conv_ttl_blo_summary.xml"/>
<outfile xil_pn:name="conv_ttl_blo_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1376472012" xil_pn:in_ck="-9057307156948659133" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1376471959">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
<outfile xil_pn:name="conv_ttl_blo.ncd"/>
<outfile xil_pn:name="conv_ttl_blo.pad"/>
<outfile xil_pn:name="conv_ttl_blo.par"/>
<outfile xil_pn:name="conv_ttl_blo.ptwx"/>
<outfile xil_pn:name="conv_ttl_blo.unroutes"/>
<outfile xil_pn:name="conv_ttl_blo.xpi"/>
<outfile xil_pn:name="conv_ttl_blo_pad.csv"/>
<outfile xil_pn:name="conv_ttl_blo_pad.txt"/>
<outfile xil_pn:name="conv_ttl_blo_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1376472048" xil_pn:in_ck="-336926714118358808" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1376472012">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<outfile xil_pn:name="conv_ttl_blo.bgn"/>
<outfile xil_pn:name="conv_ttl_blo.bit"/>
<outfile xil_pn:name="conv_ttl_blo.drc"/>
<outfile xil_pn:name="conv_ttl_blo.ut"/>
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1376472012" xil_pn:in_ck="4600148398000832422" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1376472000">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
<outfile xil_pn:name="conv_ttl_blo.twr"/>
<outfile xil_pn:name="conv_ttl_blo.twx"/>
</transform>
</transforms>
</generated_project>
hdl/regtest/syn/conv_ttl_blo.mcs 0 → 100644
View file @ b7f404e0
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/regtest/syn/conv_ttl_blo.prm 0 → 100644
View file @ b7f404e0
PROMGEN: Xilinx Prom Generator P.28xd
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
promgen -spi -w -u 0 conv_ttl_blo.bit
PROM conv_ttl_blo.prm map: Tue Aug 13 16:17:11 2013
Format Mcs86 (32-bit)
Size 2048K
PROM start 0000:0000
PROM end 001f:ffff
Addr1 Addr2 Date File(s)
0000:0000 0016:a673 Aug 13 16:15:17 2013 conv_ttl_blo.bit
hdl/regtest/syn/conv_ttl_blo.xise 0 → 100644
View file @ b7f404e0
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
</header>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
<properties>
<property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc6slx45t" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|conv_ttl_blo" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/conv_ttl_blo" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="conv_ttl_blo" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="conv_ttl_blo_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="conv_ttl_blo_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="conv_ttl_blo_synthesis.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="conv_ttl_blo_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="conv_ttl_blo" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-08-13T09:42:26" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="DC482B4272B1AF4860B418FDB8F858B4" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<libraries/>
<files>
<file xil_pn:name="../top/conv_ttl_blo.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="../top/conv_ttl_blo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="../../bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="../../bicolor_led_ctrl/bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="../../reset_gen/rtl/reset_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="../../vbcp_wb/rtl/i2c_slave_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="../../vbcp_wb/rtl/i2c_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="../../vbcp_wb/rtl/vbcp_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="../../glitch_filt/rtl/glitch_filt.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/common/gc_moving_average.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/common/gc_dual_clock_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/common/gc_wfifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/common/gc_word_packer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/common/gc_clk_div.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="30"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="32"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="33"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="34"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="35"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="36"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="37"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="38"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="39"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="40"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="41"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="42"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="43"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="44"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="45"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="46"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="47"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="48"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="49"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="50"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="51"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="52"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="53"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="54"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="55"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="56"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="57"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="58"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="59"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="60"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="61"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="62"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="63"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="64"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="65"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="66"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="67"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="68"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="69"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="70"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="71"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="72"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="73"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="74"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="75"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="76"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="77"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="78"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="79"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="80"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="81"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="82"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="83"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="84"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="85"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="86"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="87"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="88"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="89"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="90"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="91"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="92"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="93"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="94"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="95"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="96"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="97"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="98"/>
</file>
</files>
<bindings/>
<version xil_pn:ise_version="14.2" xil_pn:schema_version="2"/>
</project>
hdl/regtest/syn/regtest.ppr 0 → 100644
View file @ b7f404e0
<?xml version="1.0"?>
<Project Version="4" Minor="36">
<FileSet Dir="sources_1" File="fileset.xml"/>
<FileSet Dir="constrs_1" File="fileset.xml"/>
<FileSet Dir="sim_1" File="fileset.xml"/>
<RunSet Dir="runs" File="runs.xml"/>
<DefaultLaunch Dir="$PRUNDIR"/>
<DefaultPromote Dir="$PROMOTEDIR"/>
<Config>
<Option Name="Id" Val="e86760636aa04032b3f8aebe5c67672c"/>
<Option Name="Part" Val="xc6slx45tfgg484-3"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compxlib"/>
<Option Name="TargetLanguage" Val="VHDL"/>
<Option Name="TargetSimulator" Val="ISim"/>
<Option Name="Board" Val=""/>
<Option Name="SourceMgmtMode" Val="DisplayOnly"/>
<Option Name="ActiveSimSet" Val=""/>
<Option Name="CxlOverwriteLibs" Val="1"/>
<Option Name="CxlFuncsim" Val="1"/>
<Option Name="CxlTimesim" Val="1"/>
<Option Name="CxlCore" Val="1"/>
<Option Name="CxlEdk" Val="0"/>
<Option Name="CxlExcludeCores" Val="1"/>
<Option Name="CxlExcludeSubLibs" Val="0"/>
</Config>
</Project>
hdl/regtest/syn/run.tcl 0 → 100644
View file @ b7f404e0
project open conv_ttl_blo.xise
process run {Generate Programming File} -force rerun_all
hdl/regtest/top/Manifest.py 0 → 100644
View file @ b7f404e0
files = [
"conv_ttl_blo.ucf",
"conv_ttl_blo.vhd"
]
modules = {
"local" : [
"../../reset_gen",
"../../bicolor_led_ctrl",
"../../vbcp_wb"
],
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git"
]
}
fetchto = "../../../../../ip_cores"
hdl/regtest/top/conv_ttl_blo.ucf 0 → 100644
View file @ b7f404e0
##--==============================================================================
##-- CERN (BE-CO-HT)
##-- Glitch filter with selectable length
##--==============================================================================
##--
##-- author: Theodor Stana (t.stana@cern.ch)
##-- Carlos-Gil Soriano
##--
##-- date of creation: 2013-04-26
##--
##-- version: 1.0
##--
##-- description:
##-- This file contains the pin definitions for the CONV-TTL-BLO FPGA. The pin
##-- names reflect those of net names at the schematic level. To keep to CERN
##-- coding standards (http://www.ohwr.org/documents/24) and make the code more
##-- readable, the pin names have been lowercased and the pin type is indicated
##-- by its suffix. The suffix "_i" indicates an input pin, "_o" an output pin
##-- and "_b" a bidirectional pin.
##--
##-- An example of net name change is given below:
##-- LED_WR_OWNADDR_I2C -> led_wr_ownaddr_i2c_o
##--
##-- Apart from this, some pins have been renamed completely and do not resemble
##-- the schematics. These pins are:
##-- TTL/INV_TTL_N -> ttl_switch_n_i
##--
##-- dependencies:
##--
##-- references:
##--
##--==============================================================================
##-- GNU LESSER GENERAL PUBLIC LICENSE
##--==============================================================================
##-- This source file is free software; you can redistribute it and/or modify it
##-- under the terms of the GNU Lesser General Public License as published by the
##-- Free Software Foundation; either version 2.1 of the License, or (at your
##-- option) any later version. This source is distributed in the hope that it
##-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
##-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
##-- See the GNU Lesser General Public License for more details. You should have
##-- received a copy of the GNU Lesser General Public License along with this
##-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
##--==============================================================================
##-- last changes:
##-- 2013-04-26 Theodor Stana t.stana@cern.ch File modified
##--==============================================================================
##-- TODO: -
##--==============================================================================
##-----------------------------------------------------------------------------
##-- Default attributes
##--
##-- IOSTANDARD = "LVCMOS25"
##-- SLEW = "SLOW"
##-- DRIVE = "12"
##-----------------------------------------------------------------------------
#NET "rst_i" LOC = N20;
#NET "rst_i" IOSTANDARD = "LVCMOS33";
#NET "fpga_sysreset_n_i" LOC = L20;
NET "mr_n_o" LOC = T22;
NET "mr_n_o" IOSTANDARD = LVCMOS33;
# NET "clk20_vcxo_i" LOC = E16;
# NET "clk20_vcxo_i" TNM_NET=clk20_vcxo_i;
# TIMESPEC TSCLK20 = PERIOD "clk20_vcxo_i" 20 MHz HIGH 50 %;
NET "fpga_clk_p_i" LOC = H12;
NET "fpga_clk_n_i" LOC = G11;
##=============================================================================
##-- FRONT PANEL TTLs
##=============================================================================
##-----------------------------------------------------------------------------
##-- Status LEDs
##-----------------------------------------------------------------------------
NET "led_ctrl0_o" LOC = M18;
NET "led_ctrl0_o" IOSTANDARD = LVCMOS33;
NET "led_ctrl0_oen_o" LOC = T20;
NET "led_ctrl0_oen_o" IOSTANDARD = LVCMOS33;
NET "led_ctrl1_o" LOC = M17;
NET "led_ctrl1_o" IOSTANDARD = LVCMOS33;
NET "led_ctrl1_oen_o" LOC = U19;
NET "led_ctrl1_oen_o" IOSTANDARD = LVCMOS33;
NET "led_multicast_2_0_o" LOC = P16;
NET "led_multicast_2_0_o" IOSTANDARD = LVCMOS33;
NET "led_multicast_3_1_o" LOC = P17;
NET "led_multicast_3_1_o" IOSTANDARD = LVCMOS33;
NET "led_wr_gmt_ttl_ttln_o" LOC = N16;
NET "led_wr_gmt_ttl_ttln_o" IOSTANDARD = LVCMOS33;
NET "led_wr_link_syserror_o" LOC = R15;
NET "led_wr_link_syserror_o" IOSTANDARD = LVCMOS33;
NET "led_wr_ok_syspw_o" LOC = R16;
NET "led_wr_ok_syspw_o" IOSTANDARD = LVCMOS33;
NET "led_wr_ownaddr_i2c_o" LOC = N15;
NET "led_wr_ownaddr_i2c_o" IOSTANDARD = LVCMOS33;
##-----------------------------------------------------------------------------
##-- Front channel LEDs
##-----------------------------------------------------------------------------
# NET "pulse_front_led_n_o[1]" LOC = H5;
# NET "pulse_front_led_n_o[1]" IOSTANDARD = LVCMOS33;
# NET "pulse_front_led_n_o[1]" DRIVE = 4;
# NET "pulse_front_led_n_o[1]" SLEW = QUIETIO;
# NET "pulse_front_led_n_o[2]" LOC = J6;
# NET "pulse_front_led_n_o[2]" IOSTANDARD = LVCMOS33;
# NET "pulse_front_led_n_o[2]" DRIVE = 4;
# NET "pulse_front_led_n_o[2]" SLEW = QUIETIO;
# NET "pulse_front_led_n_o[3]" LOC = K6;
# NET "pulse_front_led_n_o[3]" IOSTANDARD = LVCMOS33;
# NET "pulse_front_led_n_o[3]" DRIVE = 4;
# NET "pulse_front_led_n_o[3]" SLEW = QUIETIO;
# NET "pulse_front_led_n_o[4]" LOC = K5;
# NET "pulse_front_led_n_o[4]" IOSTANDARD = LVCMOS33;
# NET "pulse_front_led_n_o[4]" DRIVE = 4;
# NET "pulse_front_led_n_o[4]" SLEW = QUIETIO;
# NET "pulse_front_led_n_o[5]" LOC = M7;
# NET "pulse_front_led_n_o[5]" IOSTANDARD = LVCMOS33;
# NET "pulse_front_led_n_o[5]" DRIVE = 4;
# NET "pulse_front_led_n_o[5]" SLEW = QUIETIO;
# NET "pulse_front_led_n_o[6]" LOC = M6;
# NET "pulse_front_led_n_o[6]" IOSTANDARD = LVCMOS33;
# NET "pulse_front_led_n_o[6]" DRIVE = 4;
# NET "pulse_front_led_n_o[6]" SLEW = QUIETIO;
##-----------------------------------------------------------------------------
##-- Rear LEDs
##-----------------------------------------------------------------------------
# NET "pulse_rear_led_n_o[1]" LOC = AB17;
# NET "pulse_rear_led_n_o[1]" IOSTANDARD = LVCMOS33;
# NET "pulse_rear_led_n_o[1]" DRIVE = 4;
# NET "pulse_rear_led_n_o[1]" SLEW = QUIETIO;
# NET "pulse_rear_led_n_o[2]" LOC = AB19;
# NET "pulse_rear_led_n_o[2]" IOSTANDARD = LVCMOS33;
# NET "pulse_rear_led_n_o[2]" DRIVE = 4;
# NET "pulse_rear_led_n_o[2]" SLEW = QUIETIO;
# NET "pulse_rear_led_n_o[3]" LOC = AA16;
# NET "pulse_rear_led_n_o[3]" IOSTANDARD = LVCMOS33;
# NET "pulse_rear_led_n_o[3]" DRIVE = 4;
# NET "pulse_rear_led_n_o[3]" SLEW = QUIETIO;
# NET "pulse_rear_led_n_o[4]" LOC = AA18;
# NET "pulse_rear_led_n_o[4]" IOSTANDARD = LVCMOS33;
# NET "pulse_rear_led_n_o[4]" DRIVE = 4;
# NET "pulse_rear_led_n_o[4]" SLEW = QUIETIO;
# NET "pulse_rear_led_n_o[5]" LOC = AB16;
# NET "pulse_rear_led_n_o[5]" IOSTANDARD = LVCMOS33;
# NET "pulse_rear_led_n_o[5]" DRIVE = 4;
# NET "pulse_rear_led_n_o[5]" SLEW = QUIETIO;
# NET "pulse_rear_led_n_o[6]" LOC = AB18;
# NET "pulse_rear_led_n_o[6]" IOSTANDARD = LVCMOS33;
# NET "pulse_rear_led_n_o[6]" DRIVE = 4;
# NET "pulse_rear_led_n_o[6]" SLEW = QUIETIO;
#
##-----------------------------------------------------------------------------
##-- TTL trigger I/O
##-----------------------------------------------------------------------------
# NET "fpga_input_ttl_n_i[1]" LOC = T2;
# NET "fpga_input_ttl_n_i[1]" IOSTANDARD = LVCMOS33;
# NET "fpga_input_ttl_n_i[1]" CLOCK_DEDICATED_ROUTE = FALSE;
# NET "fpga_input_ttl_n_i[2]" LOC = U3;
# NET "fpga_input_ttl_n_i[2]" IOSTANDARD = LVCMOS33;
# NET "fpga_input_ttl_n_i[2]" CLOCK_DEDICATED_ROUTE = FALSE;
# NET "fpga_input_ttl_n_i[3]" LOC = V5;
# NET "fpga_input_ttl_n_i[3]" IOSTANDARD = LVCMOS33;
# NET "fpga_input_ttl_n_i[3]" CLOCK_DEDICATED_ROUTE = FALSE;
# NET "fpga_input_ttl_n_i[4]" LOC = W4;
# NET "fpga_input_ttl_n_i[4]" IOSTANDARD = LVCMOS33;
# NET "fpga_input_ttl_n_i[4]" CLOCK_DEDICATED_ROUTE = FALSE;
# NET "fpga_input_ttl_n_i[5]" LOC = T6;
# NET "fpga_input_ttl_n_i[5]" IOSTANDARD = LVCMOS33;
# NET "fpga_input_ttl_n_i[5]" CLOCK_DEDICATED_ROUTE = FALSE;
# NET "fpga_input_ttl_n_i[6]" LOC = T3;
# NET "fpga_input_ttl_n_i[6]" IOSTANDARD = LVCMOS33;
# NET "fpga_input_ttl_n_i[6]" CLOCK_DEDICATED_ROUTE = FALSE;
#
# NET "fpga_out_ttl_o[1]" LOC = C1;
# NET "fpga_out_ttl_o[1]" IOSTANDARD = LVCMOS33;
# NET "fpga_out_ttl_o[2]" LOC = F2;
# NET "fpga_out_ttl_o[2]" IOSTANDARD = LVCMOS33;
# NET "fpga_out_ttl_o[3]" LOC = F5;
# NET "fpga_out_ttl_o[3]" IOSTANDARD = LVCMOS33;
# NET "fpga_out_ttl_o[4]" LOC = H4;
# NET "fpga_out_ttl_o[4]" IOSTANDARD = LVCMOS33;
# NET "fpga_out_ttl_o[5]" LOC = J4;
# NET "fpga_out_ttl_o[5]" IOSTANDARD = LVCMOS33;
# NET "fpga_out_ttl_o[6]" LOC = H2;
# NET "fpga_out_ttl_o[6]" IOSTANDARD = LVCMOS33;
#
##-----------------------------------------------------------------------------
##-- Inverted TTL I/O
##-----------------------------------------------------------------------------
# NET "inv_in_n_i[1]" LOC = V2;
# NET "inv_in_n_i[1]" IOSTANDARD = LVCMOS33;
# NET "inv_in_n_i[1]" CLOCK_DEDICATED_ROUTE = FALSE;
# NET "inv_in_n_i[2]" LOC = W3;
# NET "inv_in_n_i[2]" IOSTANDARD = LVCMOS33;
# NET "inv_in_n_i[2]" CLOCK_DEDICATED_ROUTE = FALSE;
# NET "inv_in_n_i[3]" LOC = Y2;
# NET "inv_in_n_i[3]" IOSTANDARD = LVCMOS33;
# NET "inv_in_n_i[3]" CLOCK_DEDICATED_ROUTE = FALSE;
# NET "inv_in_n_i[4]" LOC = AA2;
# NET "inv_in_n_i[4]" IOSTANDARD = LVCMOS33;
# NET "inv_in_n_i[4]" CLOCK_DEDICATED_ROUTE = FALSE;
# NET "inv_out_o[1]" LOC = J3;
# NET "inv_out_o[1]" IOSTANDARD = LVCMOS33;
# NET "inv_out_o[2]" LOC = L3;
# NET "inv_out_o[2]" IOSTANDARD = LVCMOS33;
# NET "inv_out_o[3]" LOC = M3;
# NET "inv_out_o[3]" IOSTANDARD = LVCMOS33;
# NET "inv_out_o[4]" LOC = P2;
# NET "inv_out_o[4]" IOSTANDARD = LVCMOS33;
##=============================================================================
##-- RTM signals
##=============================================================================
##-----------------------------------------------------------------------------
##-- Blocking I/O
##-----------------------------------------------------------------------------
# NET "fpga_blo_in_i[1]" LOC = Y9;
# NET "fpga_blo_in_i[1]" IOSTANDARD = "LVCMOS33";
# NET "fpga_blo_in_i[2]" LOC = AA10;
# NET "fpga_blo_in_i[2]" IOSTANDARD = "LVCMOS33";
# NET "fpga_blo_in_i[3]" LOC = W12;
# NET "fpga_blo_in_i[3]" IOSTANDARD = "LVCMOS33";
# NET "fpga_blo_in_i[4]" LOC = AA6;
# NET "fpga_blo_in_i[4]" IOSTANDARD = "LVCMOS33";
# NET "fpga_blo_in_i[5]" LOC = Y7;
# NET "fpga_blo_in_i[5]" IOSTANDARD = "LVCMOS33";
# NET "fpga_blo_in_i[6]" LOC = AA8;
# NET "fpga_blo_in_i[6]" IOSTANDARD = "LVCMOS33";
#
# NET "fpga_trig_blo_o[1]" LOC = W9;
# NET "fpga_trig_blo_o[1]" IOSTANDARD = "LVCMOS33";
# NET "fpga_trig_blo_o[2]" LOC = T10;
# NET "fpga_trig_blo_o[2]" IOSTANDARD = "LVCMOS33";
# NET "fpga_trig_blo_o[3]" LOC = V7;
# NET "fpga_trig_blo_o[3]" IOSTANDARD = "LVCMOS33";
# NET "fpga_trig_blo_o[4]" LOC = U9;
# NET "fpga_trig_blo_o[4]" IOSTANDARD = "LVCMOS33";
# NET "fpga_trig_blo_o[5]" LOC = T8;
# NET "fpga_trig_blo_o[5]" IOSTANDARD = "LVCMOS33";
# NET "fpga_trig_blo_o[6]" LOC = R9;
# NET "fpga_trig_blo_o[6]" IOSTANDARD = "LVCMOS33";
##=============================================================================
##-- VME CONNECTOR SIGNALS
##=============================================================================
##-----------------------------------------------------------------------------
##-- I2C lines
##-----------------------------------------------------------------------------
NET "scl_i" LOC = F19;
NET "scl_i" IOSTANDARD = LVCMOS33;
NET "scl_o" LOC = E20;
NET "scl_o" IOSTANDARD = LVCMOS33;
NET "scl_o" DRIVE = 4;
NET "scl_oe_o" LOC = H18;
NET "scl_oe_o" IOSTANDARD = LVCMOS33;
NET "scl_oe_o" DRIVE = 4;
# NET "scl_oe_o" PULLDOWN;
NET "sda_i" LOC = G20;
NET "sda_i" IOSTANDARD = LVCMOS33;
NET "sda_o" LOC = F20;
NET "sda_o" IOSTANDARD = LVCMOS33;
NET "sda_o" SLEW = FAST;
NET "sda_o" DRIVE = 4;
# NET "sda_o" PULLUP;
NET "sda_oe_o" LOC = J19;
NET "sda_oe_o" IOSTANDARD = LVCMOS33;
NET "sda_oe_o" SLEW = FAST;
NET "sda_oe_o" DRIVE = 4;
# NET "sda_oe_o" PULLDOWN;
##-----------------------------------------------------------------------------
##-- Geographical Address
##-----------------------------------------------------------------------------
NET "fpga_ga_i[0]" LOC = H20;
NET "fpga_ga_i[0]" IOSTANDARD = LVCMOS33;
NET "fpga_ga_i[1]" LOC = J20;
NET "fpga_ga_i[1]" IOSTANDARD = LVCMOS33;
NET "fpga_ga_i[2]" LOC = K19;
NET "fpga_ga_i[2]" IOSTANDARD = LVCMOS33;
NET "fpga_ga_i[3]" LOC = K20;
NET "fpga_ga_i[3]" IOSTANDARD = LVCMOS33;
NET "fpga_ga_i[4]" LOC = L19;
NET "fpga_ga_i[4]" IOSTANDARD = LVCMOS33;
NET "fpga_gap_i" LOC = H19;
NET "fpga_gap_i" IOSTANDARD = LVCMOS33;
###-----------------------------------------------------------------------------
###-- ROM memory
###-----------------------------------------------------------------------------
#NET "fpga_prom_cclk_o" LOC = Y20;
#NET "fpga_prom_cclk_o" IOSTANDARD = "LVCMOS33";
#NET "fpga_prom_cso_b_n_o" LOC = AA3;
#NET "fpga_prom_cso_b_n_o" IOSTANDARD = "LVCMOS33";
#NET "fpga_prom_miso_i" LOC = AA20;
#NET "fpga_prom_miso_i" IOSTANDARD = "LVCMOS33";
#NET "fpga_prom_mosi_o" LOC = AB20;
#NET "fpga_prom_mosi_o" IOSTANDARD = "LVCMOS33";
#
#
###=============================================================================
###-- WHITE RABBIT
###=============================================================================
###-----------------------------------------------------------------------------
###-- Thermo for UID
###-----------------------------------------------------------------------------
#NET "thermometer_b" LOC = B1;
#NET "thermometer_b" IOSTANDARD = LVCMOS33;
###-----------------------------------------------------------------------------
###-- DAC control
###-----------------------------------------------------------------------------
#NET "fpga_plldac1_din_o" LOC = AB14;
#NET "fpga_plldac1_din_o" IOSTANDARD = LVCMOS33;
#NET "fpga_plldac1_sclk_o" LOC = AA14;
#NET "fpga_plldac1_sclk_o" IOSTANDARD = LVCMOS33;
#NET "fpga_plldac1_sync_n_o" LOC = AB15;
#NET "fpga_plldac1_sync_n_o" IOSTANDARD = LVCMOS33;
#
#NET "fpga_plldac2_din_o" LOC = W14;
#NET "fpga_plldac2_din_o" IOSTANDARD = LVCMOS33;
#NET "fpga_plldac2_sclk_o" LOC = Y14;
#NET "fpga_plldac2_sclk_o" IOSTANDARD = LVCMOS33;
#NET "fpga_plldac2_sync_n_o" LOC = W13;
#NET "fpga_plldac2_sync_n_o" IOSTANDARD = LVCMOS33;
###-----------------------------------------------------------------------------
###-- SFP connection
###-----------------------------------------------------------------------------
##NET "fpga_sfp_los_i" LOC = G3;
## NET "fpga_sfp_los_i" IOSTANDARD = "LVCMOS33";
##NET "fpga_sfp_mod_def0_i" LOC = K8;
## NET "fpga_sfp_mod_def0_i" IOSTANDARD = "LVCMOS33";
##NET "fpga_sfp_rate_select_o" LOC = C4;
## NET "fpga_sfp_rate_select_o" IOSTANDARD = "LVCMOS33";
#NET "fpga_sfp_mod_def1_b" LOC = G4;
#NET "fpga_sfp_mod_def1_b" IOSTANDARD = LVCMOS33;
#
#NET "fpga_sfp_mod_def2_b" LOC = F3;
#NET "fpga_sfp_mod_def2_b" IOSTANDARD = LVCMOS33;
##NET "fpga_sfp_tx_disable_o" LOC = E4;
## NET "fpga_sfp_tx_disable_o" IOSTANDARD = "LVCMOS33";
##NET "fpga_sfp_tx_fault_i" LOC = D2;
## NET "fpga_sfp_tx_fault_i" IOSTANDARD = "LVCMOS33";
###-----------------------------------------------------------------------------
###-- FPGA MGT lines
###-----------------------------------------------------------------------------
#NET "fpga_mgt_clk0_p_i" LOC = A10;
#NET "fpga_mgt_clk0_n_i" LOC = B10;
#
#NET "mgt_sfp_rx0_p_i" LOC = D7;
#NET "mgt_sfp_rx0_n_i" LOC = C7;
#
#NET "mgt_sfp_tx0_p_o" LOC = B6;
#NET "mgt_sfp_tx0_n_o" LOC = A6;
###=============================================================================
###-- ADDITIONAL PINS
###=============================================================================
# NET "fpga_oe_o" LOC = R3;
# NET "fpga_oe_o" IOSTANDARD = LVCMOS33;
# NET "fpga_oe_o" DRIVE = 4;
# NET "fpga_oe_o" SLEW = QUIETIO;
#
# NET "fpga_blo_oe_o" LOC = P5;
# NET "fpga_blo_oe_o" IOSTANDARD = LVCMOS33;
# NET "fpga_blo_oe_o" DRIVE = 4;
# NET "fpga_blo_oe_o" SLEW = QUIETIO;
# NET "fpga_trig_ttl_oe_o" LOC = N3;
# NET "fpga_trig_ttl_oe_o" IOSTANDARD = LVCMOS33;
# NET "fpga_trig_ttl_oe_o" DRIVE = 4;
# NET "fpga_trig_ttl_oe_o" SLEW = QUIETIO;
#
# NET "fpga_inv_oe_o" LOC = P6;
# NET "fpga_inv_oe_o" IOSTANDARD = LVCMOS33;
# NET "fpga_inv_oe_o" DRIVE = 4;
# NET "fpga_inv_oe_o" SLEW = QUIETIO;
##-----------------------------------------------------------------------------
##-- Configuration Switches
##-----------------------------------------------------------------------------
# NET "extra_switch_n_i[1]" LOC = F22;
# NET "extra_switch_n_i[1]" IOSTANDARD = "LVCMOS33";
# NET "extra_switch_n_i[2]" LOC = G22;
# NET "extra_switch_n_i[2]" IOSTANDARD = "LVCMOS33";
# NET "extra_switch_n_i[3]" LOC = H21;
# NET "extra_switch_n_i[3]" IOSTANDARD = "LVCMOS33";
# NET "extra_switch_n_i[4]" LOC = H22;
# NET "extra_switch_n_i[4]" IOSTANDARD = "LVCMOS33";
# NET "extra_switch_n_i[5]" LOC = J22;
# NET "extra_switch_n_i[5]" IOSTANDARD = "LVCMOS33";
# NET "extra_switch_n_i[6]" LOC = K21;
# NET "extra_switch_n_i[6]" IOSTANDARD = "LVCMOS33";
# NET "extra_switch_n_i[7]" LOC = K22;
# NET "extra_switch_n_i[7]" IOSTANDARD = "LVCMOS33";
# NET "ttl_switch_n_i" LOC = L22;
# NET "ttl_switch_n_i" IOSTANDARD = LVCMOS33;
##-----------------------------------------------------------------------------
##-- Motherboard and piggyback IDs
##-----------------------------------------------------------------------------
# NET "fpga_rtmm_n_i[0]" LOC = V21;
# NET "fpga_rtmm_n_i[0]" IOSTANDARD = LVCMOS33;
# NET "fpga_rtmm_n_i[1]" LOC = V22;
# NET "fpga_rtmm_n_i[1]" IOSTANDARD = LVCMOS33;
# NET "fpga_rtmm_n_i[2]" LOC = U22;
# NET "fpga_rtmm_n_i[2]" IOSTANDARD = LVCMOS33;
# NET "fpga_rtmp_n_i[0]" LOC = W22;
# NET "fpga_rtmp_n_i[0]" IOSTANDARD = LVCMOS33;
# NET "fpga_rtmp_n_i[1]" LOC = Y22;
# NET "fpga_rtmp_n_i[1]" IOSTANDARD = LVCMOS33;
# NET "fpga_rtmp_n_i[2]" LOC = Y21;
# NET "fpga_rtmp_n_i[2]" IOSTANDARD = LVCMOS33;
###-----------------------------------------------------------------------------
###-- General purpose
###-----------------------------------------------------------------------------
# NET "fpga_header_out_n_o[1]" LOC = F15;
# NET "fpga_header_out_n_o[1]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[2]" LOC = F16;
# NET "fpga_header_out_n_o[2]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[3]" LOC = F17;
# NET "fpga_header_out_n_o[3]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[4]" LOC = F14;
# NET "fpga_header_out_n_o[4]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[5]" LOC = H14;
# NET "fpga_header_out_n_o[5]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[6]" LOC = H13;
# NET "fpga_header_out_n_o[6]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[1]" LOC = A17;
# NET "fpga_header_in_n_i[1]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[2]" LOC = A18;
# NET "fpga_header_in_n_i[2]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[3]" LOC = B18;
# NET "fpga_header_in_n_i[3]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[4]" LOC = A19;
# NET "fpga_header_in_n_i[4]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[5]" LOC = A20;
# NET "fpga_header_in_n_i[5]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[6]" LOC = B20;
# NET "fpga_header_in_n_i[6]" IOSTANDARD = "LVCMOS33";
# NET "cmp_i2c_bridge/i2c_addr_i[6]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/i2c_addr_i[5]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/i2c_addr_i[4]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/i2c_addr_i[3]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/i2c_addr_i[2]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/i2c_addr_i[1]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/i2c_addr_i[0]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/rx_byte[7]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/rx_byte[6]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/rx_byte[5]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/rx_byte[4]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/rx_byte[3]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/rx_byte[2]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/rx_byte[1]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/rx_byte[0]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/wb_adr[11]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/wb_adr[10]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/wb_adr[9]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/wb_adr[8]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/wb_adr[7]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/wb_adr[6]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/wb_adr[5]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/wb_adr[4]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/wb_adr[3]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/wb_adr[2]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/wb_adr[1]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/wb_adr[0]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/i2c_done_o" KEEP = "TRUE";
# NET "ram_we" KEEP = "TRUE";
# NET "xbar_master_out[0]_cyc" KEEP = "TRUE";
# NET "xbar_master_out[0]_stb" KEEP = "TRUE";
# NET "xbar_master_out[0]_we" KEEP = "TRUE";
# NET "xbar_master_out[0]_adr[11]" KEEP = "TRUE";
# NET "xbar_master_out[0]_adr[10]" KEEP = "TRUE";
# NET "xbar_master_out[0]_adr[9]" KEEP = "TRUE";
# NET "xbar_master_out[0]_adr[8]" KEEP = "TRUE";
# NET "xbar_master_out[0]_adr[7]" KEEP = "TRUE";
# NET "xbar_master_out[0]_adr[6]" KEEP = "TRUE";
# NET "xbar_master_out[0]_adr[5]" KEEP = "TRUE";
# NET "xbar_master_out[0]_adr[4]" KEEP = "TRUE";
# NET "xbar_master_out[0]_adr[3]" KEEP = "TRUE";
# NET "xbar_master_out[0]_adr[2]" KEEP = "TRUE";
# NET "xbar_master_out[0]_adr[1]" KEEP = "TRUE";
# NET "xbar_master_out[0]_adr[0]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[31]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[30]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[29]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[28]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[27]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[26]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[25]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[24]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[23]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[22]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[21]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[20]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[19]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[18]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[17]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[16]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[15]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[14]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[13]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[12]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[11]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[10]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[9]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[8]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[7]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[6]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[5]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[4]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[3]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[2]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[1]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[0]" KEEP = "TRUE";
# NET "ram_ack" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[31]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[30]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[29]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[28]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[27]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[26]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[25]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[24]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[23]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[22]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[21]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[20]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[19]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[18]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[17]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[16]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[15]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[14]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[13]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[12]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[11]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[10]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[9]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[8]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[7]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[6]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[5]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[4]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[3]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[2]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[1]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[0]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[31]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[30]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[29]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[28]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[27]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[26]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[25]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[24]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[23]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[22]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[21]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[20]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[19]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[18]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[17]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[16]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[15]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[14]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[13]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[12]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[11]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[10]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[9]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[8]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[7]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[6]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[5]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[4]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[3]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[2]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[1]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[0]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[31]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[30]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[29]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[28]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[27]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[26]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[25]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[24]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[23]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[22]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[21]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[20]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[19]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[18]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[17]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[16]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[15]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[14]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[13]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[12]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[11]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[10]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[9]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[8]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[7]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[6]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[5]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[4]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[3]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[2]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[1]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[0]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[31]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[30]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[29]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[28]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[27]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[26]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[25]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[24]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[23]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[22]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[21]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[20]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[19]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[18]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[17]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[16]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[15]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[14]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[13]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[12]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[11]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[10]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[9]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[8]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[7]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[6]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[5]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[4]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[3]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[2]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[1]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[0]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_ack" KEEP = "TRUE";
# NET "xbar_slave_in[0]_cyc" KEEP = "TRUE";
# NET "xbar_slave_in[0]_we" KEEP = "TRUE";
# NET "xbar_slave_in[0]_stb" KEEP = "TRUE";
# NET "xbar_slave_out[0]_err" KEEP = "TRUE";
hdl/regtest/top/conv_ttl_blo.vhd 0 → 100644
View file @ b7f404e0
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Top level entity of CONV-TTL-BLO
-- http://www.ohwr.org/projects/conv-ttl-blo
--------------------------------------------------------------------------------
--
-- unit name: conv_ttl_blo.vhd
--
-- author: Theodor-Adrian Stana (t.stana@cern.ch)
--
-- version: 1.0
--
-- description: Top entity of CONV-TTL-BLO
--
-- dependencies:
--
-- references:
-- [1] ELMA, Access to board data using SNMP and I2C
-- http://www.ohwr.org/documents/227
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
library ieee;
library unisim;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use unisim.vcomponents.all;
use work.bicolor_led_ctrl_pkg.all;
use work.wishbone_pkg.all;
use work.gencores_pkg.all;
use work.genram_pkg.all;
entity conv_ttl_blo is
generic
(
g_nr_ttl_chan : natural := 6;
g_nr_inv_chan : natural := 4
);
port
(
-- Clock lines
fpga_clk_p_i : in std_logic; --Using the 125MHz clock
fpga_clk_n_i : in std_logic;
-- LEDs
led_ctrl0_o : out std_logic;
led_ctrl0_oen_o : out std_logic;
led_ctrl1_o : out std_logic;
led_ctrl1_oen_o : out std_logic;
led_multicast_2_0_o : out std_logic;
led_multicast_3_1_o : out std_logic;
led_wr_gmt_ttl_ttln_o : out std_logic;
led_wr_link_syserror_o : out std_logic;
led_wr_ok_syspw_o : out std_logic;
led_wr_ownaddr_i2c_o : out std_logic;
-- Lines for the i2c_slave
scl_i : in std_logic;
scl_o : out std_logic;
scl_oe_o : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
sda_oe_o : out std_logic;
fpga_ga_i : in std_logic_vector(4 downto 0);
fpga_gap_i : in std_logic;
-- It allows power sequencing of the 24V rail after a security delay
mr_n_o : out std_logic
);
end conv_ttl_blo;
architecture behav of conv_ttl_blo is
--============================================================================
-- Constant declarations
--============================================================================
-- Number of Wishbone masters and slaves, for wb_crossbar
constant c_nr_masters : natural := 1;
constant c_nr_slaves : natural := 1;
-----------------------------------------
-- Memory map
-- * all registers are word-addressable
-- * all registers are word-aligned
-----------------------------------------
-- MEM [000-FFF]
-----------------------------------------
-- slave order definitions
constant c_slv_mem : natural := 0;
-- base address definitions
constant c_addr_mem : t_wishbone_address := x"00000000";
-- address mask definitions
constant c_mask_mem : t_wishbone_address := x"00000000";
-- addresses constant for Wishbone crossbar
constant c_addresses : t_wishbone_address_array(c_nr_slaves-1 downto 0)
:= (
c_slv_mem => c_addr_mem
);
-- masks constant for Wishbone crossbar
constant c_masks : t_wishbone_address_array(c_nr_slaves-1 downto 0)
:= (
c_slv_mem => c_mask_mem
);
--============================================================================
-- Component declarations
--============================================================================
-- Reset generator component
-- (use: global reset generation, output reset generation)
component reset_gen is
generic
(
-- Reset time in number of clk_i cycles
g_reset_time : positive := 5_000_000
);
port
(
clk_i : in std_logic;
rst_i : in std_logic;
rst_n_o : out std_logic
);
end component reset_gen;
-- I2C bridge
-- (use: convert I2C transfers into WB transfers on memmapped registers)
component vbcp_wb is
port
(
-- Clock, reset
clk_i : in std_logic;
rst_n_i : in std_logic;
-- I2C lines
sda_en_o : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
scl_en_o : out std_logic;
scl_i : in std_logic;
scl_o : out std_logic;
-- I2C address and status
i2c_addr_i : in std_logic_vector(6 downto 0);
i2c_done_o : out std_logic;
i2c_err_o : out std_logic;
-- Wishbone master signals
wbm_stb_o : out std_logic;
wbm_cyc_o : out std_logic;
wbm_sel_o : out std_logic_vector(3 downto 0);
wbm_we_o : out std_logic;
wbm_dat_i : in std_logic_vector(31 downto 0);
wbm_dat_o : out std_logic_vector(31 downto 0);
wbm_adr_o : out std_logic_vector(31 downto 0);
wbm_ack_i : in std_logic;
wbm_rty_i : in std_logic;
wbm_err_i : in std_logic
);
end component vbcp_wb;
--============================================================================
-- Signal declarations
--============================================================================
-- Clock signals
signal clk125 : std_logic;
-- Reset signals
signal rst_n, rst : std_logic;
-- Wishbone crossbar signals
signal xbar_slave_in : t_wishbone_slave_in_array (c_nr_masters - 1 downto 0);
signal xbar_slave_out : t_wishbone_slave_out_array (c_nr_masters - 1 downto 0);
signal xbar_master_in : t_wishbone_master_in_array (c_nr_slaves - 1 downto 0);
signal xbar_master_out : t_wishbone_master_out_array(c_nr_slaves - 1 downto 0);
-- RAM signals
signal ram_we : std_logic;
signal ram_ack : std_logic;
-- Signal for controlling the bicolor LED matrix
signal bicolor_led_state : std_logic_vector(23 downto 0);
-- I2C bridge signals
signal i2c_done : std_logic;
signal i2c_err : std_logic;
signal i2c_err_led : std_logic;
signal i2c_up : std_logic;
signal i2c_addr : std_logic_vector(6 downto 0);
signal led_i2c : std_logic;
signal led_i2c_clkdiv : unsigned(22 downto 0);
signal led_i2c_cnt : unsigned( 2 downto 0);
signal blink_state : std_logic;
begin
--============================================================================
-- Generate 125 MHz global signal from differential lines
--============================================================================
cmp_125_diff_buf : IBUFGDS
generic map
(
DIFF_TERM => TRUE,
IBUF_LOW_PWR => TRUE
)
port map
(
I => fpga_clk_p_i,
IB => fpga_clk_n_i,
O => clk125
);
--============================================================================
-- Internal and external reset generation
--============================================================================
-- Configure reset generator for 96ms power-on reset
cmp_reset_gen : reset_gen
generic map
(
-- Reset time: 12 * 8ns * (10**6) = 96 ms
g_reset_time => 12*(10**6)
)
port map
(
clk_i => clk125,
rst_i => '0',
rst_n_o => rst_n
);
-- rst <= not rst_n;
mr_n_o <= rst_n;
--============================================================================
-- I2C bridge logic
--============================================================================
-- Set the I2C address signal according to ELMA protocol [1]
i2c_addr <= "10" & fpga_ga_i;
-- Instantiate VBCP bridge component
cmp_i2c_bridge : vbcp_wb
port map
(
-- Clock, reset
clk_i => clk125,
rst_n_i => rst_n,
-- I2C lines
sda_en_o => sda_oe_o,
sda_i => sda_i,
sda_o => sda_o,
scl_en_o => scl_oe_o,
scl_i => scl_i,
scl_o => scl_o,
-- I2C address and status
i2c_addr_i => i2c_addr,
i2c_done_o => i2c_done,
i2c_err_o => i2c_err,
-- Wishbone master signals
wbm_stb_o => xbar_slave_in(0).stb,
wbm_cyc_o => xbar_slave_in(0).cyc,
wbm_sel_o => xbar_slave_in(0).sel,
wbm_we_o => xbar_slave_in(0).we,
wbm_dat_i => xbar_slave_out(0).dat,
wbm_dat_o => xbar_slave_in(0).dat,
wbm_adr_o => xbar_slave_in(0).adr,
wbm_ack_i => xbar_slave_out(0).ack,
wbm_rty_i => xbar_slave_out(0).rty,
wbm_err_i => xbar_slave_out(0).err
);
-- Process to blink the LED for a finite amount of time when the i2c_done
-- signal is set.
p_i2c_blink : process(clk125)
begin
if rising_edge(clk125) then
if (rst_n = '0') then
led_i2c_clkdiv <= (others => '0');
led_i2c_cnt <= (others => '0');
led_i2c <= '0';
blink_state <= '0';
else
case blink_state is
when '0' =>
led_i2c <= '0';
if (i2c_done = '1') then
blink_state <= '1';
end if;
when '1' =>
led_i2c_clkdiv <= led_i2c_clkdiv + 1;
if (led_i2c_clkdiv = 2499999) then
led_i2c_clkdiv <= (others => '0');
led_i2c_cnt <= led_i2c_cnt + 1;
led_i2c <= not led_i2c;
if (led_i2c_cnt = 7) then
led_i2c_cnt <= (others => '0');
blink_state <= '0';
end if;
end if;
when others =>
blink_state <= '0';
end case;
end if;
end if;
end process p_i2c_blink;
-- Process to set the I2C error LED signal for display on the front panel
-- of the front module. The I2C error signal is permanently set once an
-- error is detected from the bridge module.
p_i2c_err_led : process (clk125) is
begin
if rising_edge(clk125) then
if (rst_n = '0') then
i2c_err_led <= '0';
elsif (i2c_err = '1') then
i2c_err_led <= '1';
end if;
end if;
end process p_i2c_err_led;
--============================================================================
-- Instantiation and connection of the main Wishbone crossbar
--============================================================================
xbar_master_in(0).int <= '0';
xbar_master_in(0).err <= '0';
cmp_wb_crossbar : xwb_crossbar
generic map
(
g_num_masters => c_nr_masters,
g_num_slaves => c_nr_slaves,
g_registered => false,
g_address => c_addresses,
g_mask => c_masks
)
port map
(
clk_sys_i => clk125,
rst_n_i => rst_n,
slave_i => xbar_slave_in,
slave_o => xbar_slave_out,
master_i => xbar_master_in,
master_o => xbar_master_out
);
--============================================================================
-- Instantiate single-port RAM
--============================================================================
cmp_memory: generic_spram
generic map (
g_data_width => 32,
g_size => 2**12
)
port map (
rst_n_i => rst_n,
clk_i => clk125,
bwe_i => (others => '0'),
we_i => ram_we,
a_i => xbar_master_out(c_slv_mem).adr(11 downto 0),
d_i => xbar_master_out(c_slv_mem).dat,
q_o => xbar_master_in(c_slv_mem).dat
);
ram_we <= xbar_master_out(c_slv_mem).we and xbar_master_out(c_slv_mem).stb and
xbar_master_out(c_slv_mem).cyc;
xbar_master_in(c_slv_mem).ack <= ram_ack;
xbar_master_in(c_slv_mem).err <= '0';
p_ram_ack : process (clk125) is
begin
if rising_edge(clk125) then
if (rst_n = '0') then
ram_ack <= '0';
else
ram_ack <= '0';
if (xbar_master_out(c_slv_mem).stb = '1') and
(xbar_master_out(c_slv_mem).cyc = '1') then
ram_ack <= '1';
end if;
end if;
end if;
end process p_ram_ack;
--============================================================================
-- Bicolor LED matrix logic
--============================================================================
-- Bicolor LED controls, corresponding to the column orders on the
-- bicolor_led_ctrl unit.
-- WR address
bicolor_led_state( 1 downto 0) <= c_LED_OFF;
-- WR GMT
bicolor_led_state( 3 downto 2) <= c_LED_OFF;
-- WR link
bicolor_led_state( 5 downto 4) <= c_LED_OFF;
-- WR OK
bicolor_led_state( 7 downto 6) <= c_LED_OFF;
-- MULTICAST 0
bicolor_led_state( 9 downto 8) <= c_LED_OFF;
-- MULTICAST 1
bicolor_led_state(11 downto 10) <= c_LED_OFF;
-- I2C
bicolor_led_state(13 downto 12) <= c_LED_GREEN when (led_i2c = '1') else
c_LED_RED when (i2c_err_led = '1') else
c_LED_OFF;
-- State of TTL/TTL_N switch
bicolor_led_state(15 downto 14) <= c_LED_OFF;
-- System error
bicolor_led_state(17 downto 16) <= c_LED_OFF;
-- System power
bicolor_led_state(19 downto 18) <= c_LED_GREEN;
-- MULTICAST 2
bicolor_led_state(21 downto 20) <= c_LED_OFF;
-- MULTICAST 3
bicolor_led_state(23 downto 22) <= c_LED_OFF;
cmp_bicolor_led_ctrl : bicolor_led_ctrl
generic map
(
g_NB_COLUMN => 6,
g_NB_LINE => 2,
g_clk_freq => 125000000,
g_refresh_rate => 250
)
port map
(
clk_i => clk125,
rst_n_i => rst_n,
led_intensity_i => "1111111",
led_state_i => bicolor_led_state,
column_o(0) => led_wr_ownaddr_i2c_o,
column_o(1) => led_wr_gmt_ttl_ttln_o,
column_o(2) => led_wr_link_syserror_o,
column_o(3) => led_wr_ok_syspw_o,
column_o(4) => led_multicast_2_0_o,
column_o(5) => led_multicast_3_1_o,
line_o(0) => led_ctrl0_o,
line_o(1) => led_ctrl1_o,
line_oen_o(0) => led_ctrl0_oen_o,
line_oen_o(1) => led_ctrl1_oen_o
);
end behav;
hdl/release/syn/Makefile
View file @ b7f404e0
......@@ -42,9 +42,9 @@ FILES := ../top/conv_ttl_blo.ucf \
../../bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd \
../../bicolor_led_ctrl/bicolor_led_ctrl.vhd \
../../reset_gen/rtl/reset_gen.vhd \
../../elma_i2c/rtl/i2c_slave_pkg.vhd \
../../elma_i2c/rtl/i2c_slave.vhd \
../../elma_i2c/rtl/elma_i2c.vhd \
../../vbcp_wb/rtl/i2c_slave_pkg.vhd \
../../vbcp_wb/rtl/i2c_slave.vhd \
../../vbcp_wb/rtl/vbcp_wb.vhd \
../../glitch_filt/rtl/glitch_filt.vhd \
../../ctb_pulse_gen/rtl/ctb_pulse_gen.vhd \
../../rtm_detector/rtl/rtm_detector.vhd \
......
hdl/release/syn/conv_ttl_blo.gise
View file @ b7f404e0
......@@ -72,34 +72,35 @@
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1375896857" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1375896857">
<transform xil_pn:end_ts="1376471978" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1376471978">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1375896857" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1700432985017783241" xil_pn:start_ts="1375896857">
<transform xil_pn:end_ts="1376471978" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1700432985017783241" xil_pn:start_ts="1376471978">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1375896857" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-5050901284947628582" xil_pn:start_ts="1375896857">
<transform xil_pn:end_ts="1376471978" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-5050901284947628582" xil_pn:start_ts="1376471978">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1375896857" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1375896857">
<transform xil_pn:end_ts="1376471978" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1376471978">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1375896857" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2180482239361632071" xil_pn:start_ts="1375896857">
<transform xil_pn:end_ts="1376471978" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2180482239361632071" xil_pn:start_ts="1376471978">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1375896857" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1375896857">
<transform xil_pn:end_ts="1376471978" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1376471978">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1375896857" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-6206634123545964380" xil_pn:start_ts="1375896857">
<transform xil_pn:end_ts="1376471978" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-6206634123545964380" xil_pn:start_ts="1376471978">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1375896876" xil_pn:in_ck="4832372736998027881" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8267614965335338665" xil_pn:start_ts="1375896857">
<transform xil_pn:end_ts="1376471999" xil_pn:in_ck="-159470544935230363" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8267614965335338665" xil_pn:start_ts="1376471978">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -117,11 +118,11 @@
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1375896876" xil_pn:in_ck="3498961748663175870" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3953035127305197084" xil_pn:start_ts="1375896876">
<transform xil_pn:end_ts="1376471999" xil_pn:in_ck="3498961748663175870" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3953035127305197084" xil_pn:start_ts="1376471999">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1375896886" xil_pn:in_ck="4600148398000832553" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7879307074684351365" xil_pn:start_ts="1375896876">
<transform xil_pn:end_ts="1376472010" xil_pn:in_ck="4600148398000832553" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7879307074684351365" xil_pn:start_ts="1376471999">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
......@@ -130,7 +131,7 @@
<outfile xil_pn:name="conv_ttl_blo.ngd"/>
<outfile xil_pn:name="conv_ttl_blo_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1375896940" xil_pn:in_ck="4600148398000832554" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1375896886">
<transform xil_pn:end_ts="1376472062" xil_pn:in_ck="4600148398000832554" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1376472010">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
......@@ -143,7 +144,7 @@
<outfile xil_pn:name="conv_ttl_blo_summary.xml"/>
<outfile xil_pn:name="conv_ttl_blo_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1375896995" xil_pn:in_ck="-9057307156948659133" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1375896940">
<transform xil_pn:end_ts="1376472115" xil_pn:in_ck="-9057307156948659133" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1376472062">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
......@@ -157,7 +158,7 @@
<outfile xil_pn:name="conv_ttl_blo_pad.txt"/>
<outfile xil_pn:name="conv_ttl_blo_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1375897030" xil_pn:in_ck="-336926714118358808" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1375896995">
<transform xil_pn:end_ts="1376472151" xil_pn:in_ck="-336926714118358808" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1376472115">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -169,7 +170,7 @@
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1375896995" xil_pn:in_ck="4600148398000832422" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1375896984">
<transform xil_pn:end_ts="1376472115" xil_pn:in_ck="4600148398000832422" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1376472104">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......
hdl/release/syn/conv_ttl_blo.xise
View file @ b7f404e0
......@@ -351,13 +351,13 @@
<file xil_pn:name="../../reset_gen/rtl/reset_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="../../elma_i2c/rtl/i2c_slave_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../vbcp_wb/rtl/i2c_slave_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="../../elma_i2c/rtl/i2c_slave.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../vbcp_wb/rtl/i2c_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="../../elma_i2c/rtl/elma_i2c.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../vbcp_wb/rtl/vbcp_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="../../glitch_filt/rtl/glitch_filt.vhd" xil_pn:type="FILE_VHDL">
......
hdl/release/top/Manifest.py
View file @ b7f404e0
......@@ -7,7 +7,7 @@ modules = {
"local" : [
"../../reset_gen",
"../rtl",
"../../elma_i2c",
"../../vbcp_wb",
"../../ctb_pulse_gen",
"../../rtm_detector",
"../../bicolor_led_ctrl",
......
hdl/release/top/conv_ttl_blo.vhd
View file @ b7f404e0
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Top level entity of CONV-TTL-BLO V2
-- Top level entity of CONV-TTL-BLO
-- http://www.ohwr.org/projects/conv-ttl-blo
--------------------------------------------------------------------------------
--
......@@ -10,7 +10,7 @@
--
-- version: 1.0
--
-- description: Top entity of CONV-TTL-BLO V1
-- description: Top entity of CONV-TTL-BLO
--
-- dependencies:
--
......@@ -31,12 +31,12 @@
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
library IEEE;
library ieee;
library unisim;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use UNISIM.VCOMPONENTS.ALL;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use unisim.vcomponents.all;
use work.bicolor_led_ctrl_pkg.all;
use work.wishbone_pkg.all;
......@@ -241,7 +241,7 @@ architecture behav of conv_ttl_blo is
-- I2C bridge
-- (use: convert I2C transfers into WB transfers on memmapped registers)
component elma_i2c is
component vbcp_wb is
port
(
-- Clock, reset
......@@ -273,7 +273,7 @@ architecture behav of conv_ttl_blo is
wbm_rty_i : in std_logic;
wbm_err_i : in std_logic
);
end component elma_i2c;
end component vbcp_wb;
component conv_regs is
port (
......@@ -419,8 +419,8 @@ begin
-- Set the I2C address signal according to ELMA protocol [1]
i2c_addr <= "10" & fpga_ga_i;
-- Instantiate I2C bridge component
cmp_i2c_bridge : elma_i2c
-- Instantiate VBCP bridge component
cmp_i2c_bridge : vbcp_wb
port map
(
-- Clock, reset
......
hdl/elma_i2c/rtl/Manifest.py → hdl/vbcp_wb/rtl/Manifest.py
View file @ b7f404e0
files = [
"i2c_slave_pkg.vhd",
"i2c_slave.vhd",
"elma_i2c.vhd"
"vbcp_wb.vhd"
]
modules = {
......
hdl/elma_i2c/rtl/elma_i2c.vhd → hdl/vbcp_wb/rtl/vbcp_wb.vhd
View file @ b7f404e0
--==============================================================================
-- CERN (BE-CO-HT)
-- I2C to Wishbone bridge for VME64x crates
-- VME Board Control Protocol (VBCP) to Wishbone bridge for VME64x crates
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
......@@ -58,7 +58,7 @@ use ieee.numeric_std.all;
use work.i2c_slave_pkg.all;
entity elma_i2c is
entity vbcp_wb is
port
(
-- Clock, reset
......@@ -90,9 +90,9 @@ entity elma_i2c is
wbm_rty_i : in std_logic;
wbm_err_i : in std_logic
);
end entity elma_i2c;
end entity vbcp_wb;
architecture behav of elma_i2c is
architecture behav of vbcp_wb is
--============================================================================
-- Type declarations
......
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