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Conv TTL Blocking - Gateware
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Conv TTL Blocking - Gateware
Commits
722ce2ed
Commit
722ce2ed
authored
Oct 22, 2013
by
Theodor-Adrian Stana
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updated vbcp_wb documentation
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fsm.pdf
doc/vbcp_wb/fig/fsm.pdf
+0
-0
fsm.svg
doc/vbcp_wb/fig/fsm.svg
+56
-10
writemregs.pdf
doc/vbcp_wb/fig/writemregs.pdf
+0
-0
writemregs.svg
doc/vbcp_wb/fig/writemregs.svg
+254
-0
vbcp_wb.pdf
doc/vbcp_wb/vbcp_wb.pdf
+0
-0
vbcp_wb.tex
doc/vbcp_wb/vbcp_wb.tex
+68
-62
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doc/vbcp_wb/fig/fsm.pdf
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doc/vbcp_wb/fig/fsm.svg
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722ce2ed
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doc/vbcp_wb/fig/writemregs.pdf
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doc/vbcp_wb/fig/writemregs.svg
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doc/vbcp_wb/vbcp_wb.pdf
View file @
722ce2ed
No preview for this file type
doc/vbcp_wb/vbcp_wb.tex
View file @
722ce2ed
...
...
@@ -42,6 +42,8 @@
\hline
26-06-2013
&
0.01
&
First draft
\\
14-08-2013
&
0.02
&
Second draft
\\
22-10-2013
&
0.03
&
Added
\textit
{
Access commands
}
section, updated document according to
changes in protocol
\\
\hline
\end{tabular}
}
...
...
@@ -125,10 +127,11 @@ Wishbone master interface ports, prefixed with \textit{wbm}.
scl
\_
i
&
1
&
SCL line input
\\
scl
\_
o
&
1
&
SCL line output
\\
i2c
\_
addr
\_
i
&
7
&
VBCP slave address on ELMA VBCP bus
\\
i2c
\_
done
\_
o
&
1
&
High for one clk
\_
i cycle when an VBCP transfer is finished
\\
i2c
\_
err
\_
o
&
1
&
High for one clk
\_
i cycle when an error occurs in the ELMA protocol
or an attempt is made to access an non-existing register on the
Wishbone bus
\\
tip
\_
o
&
1
&
Transfer In Progress
\newline
'1' -- I
$^
2
$
C address sent by SysMon matches that of the VBCP slave
\newline
'0' -- after transfer has completed and VBCP slave is idle
\\
err
\_
o
&
1
&
Error bit, high for one
\textit
{
clk
\_
i
}
cycle when the Wishbone address
the SysMon tries to access is invalid
\\
wbm
\_
stb
\_
o
&
1
&
Wishbone data strobe output
\\
wbm
\_
cyc
\_
o
&
1
&
Wishbone valid cycle output
\\
wbm
\_
sel
\_
o
&
4
&
Wishbone byte select output
\\
...
...
@@ -192,66 +195,16 @@ Wishbone master interface ports, prefixed with \textit{wbm}.
After proper synthesis and download to the FPGA, a Telnet or serial connection
should be made to the SysMon board. Commands can then be sent to the boards via
the SysMon. The two commands relevant for accessing board registers are
\textit
{
readreg
}
and
\textit
{
writereg
}
, outlined in Table~
\ref
{
tbl:cmds
}
.
\begin{table}
[h]
\caption
{
The
\textit
{
readreg
}
and
\textit
{
writereg
}
commands
}
\label
{
tbl:cmds
}
\centerline
{
\begin{tabular}
{
l p
{
.6
\textwidth
}}
\hline
\multicolumn
{
1
}{
c
}{
\textbf
{
Command
}}
&
\multicolumn
{
1
}{
c
}{
\textbf
{
Description
}}
\\
\hline
writereg
\textit
{
slot reg val
}
&
Writes the
\textit
{
hex
}
value
\textit
{
val
}
to register number
\textit
{
reg
}
of board in slot number
\textit
{
slot
}
\\
readreg
\textit
{
slot reg
}
&
Returns the value of register number
\textit
{
reg
}
of
board in slot number
\textit
{
slot
}
\\
\hline
\end{tabular}
}
\end{table}
Register (
\textit
{
reg
}
) numbers in these commands are decimal numbers starting from 1.
The SysMon translates
\textit
{
reg
}
numbers into word-aligned addresses, thus in order
to obtain the actual register addres, the following relation should be used:
\begin{center}
$
addr
=
(
reg
-
1
)*
4
$
\end{center}
Table~
\ref
{
tbl:reg
}
shows the
\textit
{
reg
}
numbers of registers in the address
space 0x00 to 0x20.
\begin{table}
[h]
\caption
{
Translating
\textit
{
reg
}
numbers to addresses
}
\label
{
tbl:reg
}
\centerline
{
\begin{tabular}
{
c c
}
\hline
\textbf
{
\textit
{
reg
}}
&
\textbf
{
Address
}
\\
\hline
1
&
0x00
\\
2
&
0x04
\\
3
&
0x08
\\
4
&
0x0C
\\
5
&
0x10
\\
6
&
0x14
\\
7
&
0x18
\\
8
&
0x1C
\\
9
&
0x20
\\
\hline
\end{tabular}
}
\end{table}
the SysMon. The two commands relevant for this basic test are
\textit
{
readreg
}
and
\textit
{
writereg
}
. These and other commands relevant for accessing board
registers are outlined in Section~
\ref
{
sec:vbcp-cmds
}
.
The example below shows how to connect to an ELMA crate at IP address 1.2.3.4,
obtaining the value of a register at address 0x10 in a board in VME slot 2,
writing the hex value 0x1234 to the same register and reading it back to check for
proper modification.
\pagebreak
\begin{verbatim}
$
telnet
1
.
2
.
3
.
4
Trying
1
.
2
.
3
.
4
...
...
...
@@ -259,21 +212,24 @@ Connected to 1.2.3.4.
Escape character is '
^
]
'.
login:user
password:
**********
%>readreg 2
5
%>readreg 2
10
Read Data:
00
ABCDEF
%>writereg 2
5
1234
%>writereg 2
10
1234
Done
!
%>readreg 2
5
%>readreg 2
10
Read Data:
00001234
\end
{
verbatim
}
%==============================================================================
% SEC: Protocol
%==============================================================================
\pagebreak
\section
{
The VME Board Control Protocol
}
\label
{
sec:vbcp
}
%------------------------------------------------------------------------------
\subsection
{
Protocol details
}
\label
{
sec:vbcp
-
prot
}
The VME backplane provides two serial lines
(
\textit
{
SERCLK
}
and
\textit
{
SERDAT
}
)
on the P
1
connector. These lines can be used to access boards placed in a VME
slots to control them, in cases where the VME interface is not implemented.
...
...
@@ -311,6 +267,56 @@ the transfer direction changes and the SysMon will read the four data
bytes sent by the VME board. As with the write transfer, the data bytes
are sent by the VME board in big
-
endian order.
%------------------------------------------------------------------------------
\subsection
{
Access commands
}
\label
{
sec:vbcp
-
cmds
}
In order to send data to a VME board using VBCP, a user connects to the SysMon
via Telnet and sends commands which the SysMon translates into I
$^
2
$
C accesses
as outlined in the previous section. The commands supported by the
\textit
{
vbcp
\_
wb
}
module are shown in Table~
\ref
{
tbl:cmds
}
.
\begin
{
table
}
[
h
]
\caption
{
The
\textit
{
readreg
}
and
\textit
{
writereg
}
commands
}
\label
{
tbl:cmds
}
\centerline
{
\begin
{
tabular
}{
l p
{
.
6
\textwidth
}}
\hline
\multicolumn
{
1
}{
c
}{
\textbf
{
Command
}}
&
\multicolumn
{
1
}{
c
}{
\textbf
{
Description
}}
\\
\hline
writereg slot addr val
&
Writes the
\textit
{
hex
}
value
\textit
{
val
}
to hex address
\textit
{
addr
}
of board in slot number
\textit
{
slot
}
\\
writemregs slot addr v
1
.. v
8
&
This command is similar to the
\textit
{
writereg
}
command, but it allows writing up to eight different values
to the same Wishbone register. The values are given in hexadecimal
format and are separate by spaces
\\
readreg slot addr
&
Returns the value of register at hex address
\textit
{
addr
}
of
board in slot number
\textit
{
slot
}
\\
\hline
\end
{
tabular
}
}
\end
{
table
}
One noteworthy subject here is the
\textit
{
writemregs
}
command. This command allows
writing more up to eight words to the same Wishbone register. It is useful
when one wants to use a Wishbone register as a proxy for accessing an on
-
board
peripheral where large amounts of data are to be written. An external memory is a
good example of such a peripheral.
\begin
{
figure
}
\centerline
{
\includegraphics
[
width
=
\textwidth
]
{
fig
/
writemregs
}}
\caption
{
SysMon write using
\textit
{
writemregs
}}
\label
{
fig:writemregs
}
\end
{
figure
}
In principle, the
\textit
{
writemregs
}
is a
\textit
{
writereg
}
with multiple data words
packed together, as outlined in Figure~
\ref
{
fig:writemregs
}
. In this figure, each data word
is split in four bytes as outlined in Figure~
\ref
{
fig:sysmon
-
wr
}
, with an ACK sent by
the VME board after every byte.
As Figure~
\ref
{
fig:writemregs
}
shows, the data words are sent in little
-
endian order,
word
0
is sent first, followed by word
1
and so forth, until word
7
.
%==============================================================================
% SEC: Implem
...
...
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