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Conv TTL Blocking - Gateware
Commit 1253636a authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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added xil_multiboot to test_pulse project

parent 148ce7b6
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hdl/release/syn/conv_ttl_blo.gise
View file @ 1253636a
......@@ -137,6 +137,8 @@
<transform xil_pn:end_ts="1382450282" xil_pn:in_ck="4600148398000832554" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1382450228">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<outfile xil_pn:name="conv_ttl_blo.pcf"/>
<outfile xil_pn:name="conv_ttl_blo_map.map"/>
......
hdl/test_pulse/syn/Makefile
View file @ 1253636a
......@@ -49,6 +49,10 @@ FILES := ../top/conv_ttl_blo.ucf \
../../vbcp_wb/rtl/vbcp_wb.vhd \
../../glitch_filt/rtl/glitch_filt.vhd \
../../pulse_gen_gp/rtl/pulse_gen_gp.vhd \
../../multiboot/rtl/multiboot_regs.vhd \
../../multiboot/rtl/multiboot_fsm.vhd \
../../multiboot/rtl/spi_master.vhd \
../../multiboot/rtl/xil_multiboot.vhd \
../../../../../ip_cores/general-cores/modules/common/gencores_pkg.vhd \
../../../../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd \
../../../../../ip_cores/general-cores/modules/common/gc_moving_average.vhd \
......
hdl/test_pulse/syn/conv_ttl_blo.gise
View file @ 1253636a
......@@ -30,6 +30,7 @@
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="conv_ttl_blo.bgn" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:fileType="FILE_BIN" xil_pn:name="conv_ttl_blo.bin"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="conv_ttl_blo.bit" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="conv_ttl_blo.bld"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="conv_ttl_blo.cmd_log"/>
......@@ -52,6 +53,7 @@
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="conv_ttl_blo.ut" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:fileType="FILE_XPI" xil_pn:name="conv_ttl_blo.xpi"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="conv_ttl_blo.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="conv_ttl_blo_envsettings.html"/>
<file xil_pn:fileType="FILE_NCD" xil_pn:name="conv_ttl_blo_guide.ncd" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="conv_ttl_blo_map.map" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="conv_ttl_blo_map.mrp" xil_pn:subbranch="Map"/>
......@@ -62,6 +64,7 @@
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="conv_ttl_blo_pad.csv" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="conv_ttl_blo_pad.txt" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="conv_ttl_blo_par.xrpt"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="conv_ttl_blo_summary.html"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="conv_ttl_blo_summary.xml"/>
<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="conv_ttl_blo_usage.xml"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="conv_ttl_blo_xst.xrpt"/>
......@@ -100,7 +103,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1379409237" xil_pn:in_ck="946591740309691062" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8267614965335338665" xil_pn:start_ts="1379409214">
<transform xil_pn:end_ts="1382452837" xil_pn:in_ck="6118850150238794815" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8267614965335338665" xil_pn:start_ts="1382452812">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -122,7 +125,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1379409247" xil_pn:in_ck="4600148398000832553" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7879307074684351365" xil_pn:start_ts="1379409237">
<transform xil_pn:end_ts="1382452844" xil_pn:in_ck="4600148398000832553" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7879307074684351365" xil_pn:start_ts="1382452837">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
......@@ -131,7 +134,7 @@
<outfile xil_pn:name="conv_ttl_blo.ngd"/>
<outfile xil_pn:name="conv_ttl_blo_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1379409344" xil_pn:in_ck="4600148398000832554" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1379409247">
<transform xil_pn:end_ts="1382452953" xil_pn:in_ck="4600148398000832554" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1382452844">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
......@@ -144,8 +147,9 @@
<outfile xil_pn:name="conv_ttl_blo_summary.xml"/>
<outfile xil_pn:name="conv_ttl_blo_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1379409414" xil_pn:in_ck="-9057307156948659133" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1379409344">
<transform xil_pn:end_ts="1382453024" xil_pn:in_ck="-9057307156948659133" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1382452953">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
<outfile xil_pn:name="conv_ttl_blo.ncd"/>
......@@ -158,18 +162,20 @@
<outfile xil_pn:name="conv_ttl_blo_pad.txt"/>
<outfile xil_pn:name="conv_ttl_blo_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1379409454" xil_pn:in_ck="-336926714118358808" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1379409414">
<transform xil_pn:end_ts="1382453347" xil_pn:in_ck="-336926714118358808" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="3952527596078283548" xil_pn:start_ts="1382453308">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<outfile xil_pn:name="conv_ttl_blo.bgn"/>
<outfile xil_pn:name="conv_ttl_blo.bin"/>
<outfile xil_pn:name="conv_ttl_blo.bit"/>
<outfile xil_pn:name="conv_ttl_blo.drc"/>
<outfile xil_pn:name="conv_ttl_blo.ut"/>
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1379409414" xil_pn:in_ck="4600148398000832422" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1379409401">
<transform xil_pn:end_ts="1382453024" xil_pn:in_ck="4600148398000832422" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1382453013">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......
hdl/test_pulse/syn/conv_ttl_blo.xise
View file @ 1253636a
This diff is collapsed.
hdl/test_pulse/top/Manifest.py
View file @ 1253636a
......@@ -9,6 +9,7 @@ modules = {
"../../bicolor_led_ctrl",
"../../vbcp_wb",
"../../pulse_gen_gp",
"../../multiboot",
"../rtl"
],
"git" : [
......
hdl/test_pulse/top/conv_ttl_blo.ucf
View file @ 1253636a
......@@ -296,19 +296,18 @@ NET "fpga_ga_i[4]" IOSTANDARD = LVCMOS33;
NET "fpga_gap_i" LOC = H19;
NET "fpga_gap_i" IOSTANDARD = LVCMOS33;
###-----------------------------------------------------------------------------
###-- ROM memory
###-----------------------------------------------------------------------------
#NET "fpga_prom_cclk_o" LOC = Y20;
#NET "fpga_prom_cclk_o" IOSTANDARD = "LVCMOS33";
#NET "fpga_prom_cso_b_n_o" LOC = AA3;
#NET "fpga_prom_cso_b_n_o" IOSTANDARD = "LVCMOS33";
#NET "fpga_prom_miso_i" LOC = AA20;
#NET "fpga_prom_miso_i" IOSTANDARD = "LVCMOS33";
#NET "fpga_prom_mosi_o" LOC = AB20;
#NET "fpga_prom_mosi_o" IOSTANDARD = "LVCMOS33";
#
#
##-----------------------------------------------------------------------------
##-- ROM memory
##-----------------------------------------------------------------------------
NET "fpga_prom_cclk_o" LOC = Y20;
NET "fpga_prom_cclk_o" IOSTANDARD = "LVCMOS33";
NET "fpga_prom_cso_b_n_o" LOC = AA3;
NET "fpga_prom_cso_b_n_o" IOSTANDARD = "LVCMOS33";
NET "fpga_prom_miso_i" LOC = AA20;
NET "fpga_prom_miso_i" IOSTANDARD = "LVCMOS33";
NET "fpga_prom_mosi_o" LOC = AB20;
NET "fpga_prom_mosi_o" IOSTANDARD = "LVCMOS33";
###=============================================================================
###-- WHITE RABBIT
###=============================================================================
......
hdl/test_pulse/top/conv_ttl_blo.vhd
View file @ 1253636a
......@@ -98,6 +98,12 @@ entity conv_ttl_blo is
fpga_ga_i : in std_logic_vector(4 downto 0);
fpga_gap_i : in std_logic;
-- Flash memory lines
fpga_prom_cclk_o : out std_logic;
fpga_prom_cso_b_n_o : out std_logic;
fpga_prom_mosi_o : out std_logic;
fpga_prom_miso_i : in std_logic;
-- It allows power sequencing of the 24V rail after a security delay
mr_n_o : out std_logic
);
......@@ -123,40 +129,43 @@ architecture behav of conv_ttl_blo is
-- Number of Wishbone masters and slaves, for wb_crossbar
constant c_nr_masters : natural := 1;
constant c_nr_slaves : natural := 3;
constant c_nr_slaves : natural := 4;
-----------------------------------------
-- Memory map
-- * all registers are word-addressable
-- * all registers are word-aligned
-----------------------------------------
-- MEM [000-FFF]
-- CONV_REGS [0x000-0x004]
-- PULSE_CNT [0x100-0x13F]
-- PGEN_CTRL [0x200-0x24F]
-- MULTIBOOT [0x300-0x31F]
-----------------------------------------
-- slave order definitions
constant c_slv_conv_regs : natural := 0;
constant c_slv_pulse_cnt : natural := 1;
constant c_slv_pgen_ctrl : natural := 2;
-- constant c_slv_mem : natural := 2;
constant c_slv_multiboot : natural := 3;
-- base address definitions
constant c_addr_conv_regs : t_wishbone_address := x"00000000";
constant c_addr_pulse_cnt : t_wishbone_address := x"00000100";
constant c_addr_pgen_ctrl : t_wishbone_address := x"00000200";
-- constant c_addr_mem : t_wishbone_address := x"00000100";
constant c_addr_multiboot : t_wishbone_address := x"00000300";
-- address mask definitions
constant c_mask_conv_regs : t_wishbone_address := x"00000F00";
constant c_mask_pulse_cnt : t_wishbone_address := x"00000F00";
constant c_mask_pgen_ctrl : t_wishbone_address := x"00000F00";
-- constant c_mask_mem : t_wishbone_address := x"00000F00";
constant c_mask_multiboot : t_wishbone_address := x"00000F00";
-- addresses constant for Wishbone crossbar
constant c_addresses : t_wishbone_address_array(c_nr_slaves-1 downto 0)
:= (
c_slv_conv_regs => c_addr_conv_regs,
c_slv_pulse_cnt => c_addr_pulse_cnt,
c_slv_pgen_ctrl => c_addr_pgen_ctrl
-- c_slv_mem => c_addr_mem
c_slv_pgen_ctrl => c_addr_pgen_ctrl,
c_slv_multiboot => c_addr_multiboot
);
-- masks constant for Wishbone crossbar
......@@ -164,8 +173,8 @@ architecture behav of conv_ttl_blo is
:= (
c_slv_conv_regs => c_mask_conv_regs,
c_slv_pulse_cnt => c_mask_pulse_cnt,
c_slv_pgen_ctrl => c_mask_pgen_ctrl
--c_slv_mem => c_mask_mem
c_slv_pgen_ctrl => c_mask_pgen_ctrl,
c_slv_multiboot => c_addr_multiboot
);
--============================================================================
......@@ -206,8 +215,8 @@ architecture behav of conv_ttl_blo is
-- I2C address and status
i2c_addr_i : in std_logic_vector(6 downto 0);
i2c_done_o : out std_logic;
i2c_err_o : out std_logic;
tip_o : out std_logic;
err_o : out std_logic;
-- Wishbone master signals
wbm_stb_o : out std_logic;
......@@ -223,6 +232,27 @@ architecture behav of conv_ttl_blo is
);
end component vbcp_wb;
-- Xilinx MultiBoot component
-- (use: remote reprogramming of the FPGA)
component xil_multiboot is
port
(
-- Clock and reset input ports
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone ports
wbs_i : in t_wishbone_slave_in;
wbs_o : out t_wishbone_slave_out;
-- SPI ports
spi_cs_n_o : out std_logic;
spi_sclk_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic
);
end component xil_multiboot;
-- Converter registers
-- (use: ID, firmware version)
component conv_regs is
......@@ -391,8 +421,8 @@ architecture behav of conv_ttl_blo is
signal bicolor_led_state : std_logic_vector(23 downto 0);
-- VBCP bridge signals
signal i2c_done : std_logic;
signal i2c_err : std_logic;
signal vbcp_tip : std_logic;
signal vbcp_err : std_logic;
signal i2c_err_led : std_logic;
signal i2c_up : std_logic;
signal i2c_addr : std_logic_vector(6 downto 0);
......@@ -487,8 +517,8 @@ begin
-- I2C address and status
i2c_addr_i => i2c_addr,
i2c_done_o => i2c_done,
i2c_err_o => i2c_err,
tip_o => vbcp_tip,
err_o => vbcp_err,
-- Wishbone master signals
wbm_stb_o => xbar_slave_in(0).stb,
......@@ -503,7 +533,7 @@ begin
wbm_err_i => xbar_slave_out(0).err
);
-- Process to blink the LED for a finite amount of time when the i2c_done
-- Process to blink the LED for a finite amount of time when the vbcp_tip
-- signal is set.
p_i2c_blink : process(clk125)
begin
......@@ -518,7 +548,7 @@ begin
when '0' =>
led_i2c <= '0';
if (i2c_done = '1') then
if (vbcp_tip = '1') then
blink_state <= '1';
end if;
......@@ -550,7 +580,7 @@ begin
if rising_edge(clk125) then
if (rst_n = '0') then
i2c_err_led <= '0';
elsif (i2c_err = '1') then
elsif (vbcp_err = '1') then
i2c_err_led <= '1';
end if;
end if;
......@@ -857,6 +887,28 @@ begin
--============================================================================
inv_out_o <= inv_in_n_i;
--============================================================================
-- MultiBoot logic
--============================================================================
xbar_master_in(c_slv_multiboot).int <= '0';
xbar_master_in(c_slv_multiboot).rty <= '0';
xbar_master_in(c_slv_multiboot).err <= '0';
cmp_multiboot : xil_multiboot
port map
(
clk_i => clk125,
rst_n_i => rst_n,
wbs_i => xbar_master_out(c_slv_multiboot),
wbs_o => xbar_master_in(c_slv_multiboot),
spi_cs_n_o => fpga_prom_cso_b_n_o,
spi_sclk_o => fpga_prom_cclk_o,
spi_mosi_o => fpga_prom_mosi_o,
spi_miso_i => fpga_prom_miso_i
);
--============================================================================
-- Bicolor LED matrix logic
--============================================================================
......
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